1
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
FEBRUARY 2002
2002 Integrated Device Technology, Inc.
DSC 5870/4
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 6MHz to 200MHz
Output frequency: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
sO E
1Q
0
Skew
Select
1Q
1
1F1:0
3
3
2Q
0
Skew
Select
2Q
1
2F1:0
FS
3
REF
PLL
FB
3
3
3Q
0
Skew
Select
3Q
1
3F1:0
3
3
4Q
0
4Q
1
Skew
Select
4F1:0
3
3
PE TEST
3
IDT5V9950
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCKTM II JR.
DESCRIPTION:
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9950 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the sOE pin is held low, all the outputs are synchronously enabled.
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V9950 has
LVTTL outputs with 12mA balanced drive outputs.
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
V
DDQ
, V
DD
Supply Voltage to Ground
0.5 to +4.6
V
V
I
DC Input Voltage
0.5 to V
DD
+0.5
V
REF Input Voltage
0.5 to +5.5
V
Maximum Power
T
A
= 85C
0.7
W
Dissipation
T
A
= 55C
1.1
T
STG
Storage Temperature Range
65 to +150
C
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF
[1:0]
, and DS
[1:0]
.
CAPACITANCE
(T
A
= +25C, f = 1MHz, V
IN
= 0V)
Parameter
Description
Typ.
Max.
Unit
C
IN
Input Capacitance
5
7
pF
31
10
3
Q
1
30
29
28
27
26
25
11
12
13
14
15
16
F
S
R
E
F
G
N
D
T
E
S
T
2
F
1
3
Q
0
F
B
2
Q
1
2
Q
0
V
D
D
Q
V
D
D
Q
V
D
D
32
9
3
F
0
G
N
D
2
F
0
1
2
3
4
5
6
7
8
3F
1
4F
0
4F
1
PE
4Q
1
4Q
0
G ND
V
D D Q
18
GND
24
23
22
21
20
19
sO E
1F
1
1F
0
1Q
0
1Q
1
V
D D Q
17
GND
TQFP
TOP VIEW
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active
with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[
1:0
] = LL.
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
FB
IN
Feedback Input
TEST
(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
sOE
(1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q
0
and 2Q
1
) in a LOW state (for PE = H) - 2Q
0
and 2Q
1
may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[
1:0
] pins act as output
disable controls for individual banks when nF[
1:0
] = LL. Set sOE LOW for normal operation (has internal pull-down).
PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
nF
[1:0]
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS
IN
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
nQ
[1:0]
OUT
Four banks of two outputs with programmable skew
V
DDQ
PWR
Power supply for output buffers
V
DD
PWR
Power supply for phase locked loop, lock output, and other internal circuitry
GND
PWR
Ground
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from 625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
PROGRAMMABLE SKEW
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V9950 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as VCO when the output connected to
FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided output
as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed 4t
U
in addition to whatever skew value is programmed for those outputs. `Max adjustment' range
applies to output pairs 3 and 4 where 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FS = LOW
FS = MID
FS = HIGH
Comments
Timing Unit Calculation (t
U
)
1/(32 x F
NOM
)
1/(16 x F
NOM
)
1/(8 x F
NOM
)
VCO Frequency Range (F
NOM
)
(1,2)
24 to 50MHz
48 to 100MHz
96 to 200MHz
Skew Adjustment Range
(3)
Max Adjustment:
7.8125ns
7.8125ns
7.8125ns
ns
67.5
135
270
Phase Degrees
18.75%
37.5%
75%
% of Cycle Time
Example 1, F
NOM
= 25MHz
t
U
= 1.25ns
--
--
Example 2, F
NOM
= 37.5MHz
t
U
= 0.833ns
--
--
Example 3, F
NOM
= 50MHz
t
U
= 0.625ns
t
U
= 1.25ns
--
Example 4, F
NOM
= 75MHz
--
t
U
= 0.833ns
--
Example 5, F
NOM
= 100MHz
--
t
U
= 0.625ns
t
U
= 1.25ns
Example 6, F
NOM
= 150MHz
--
--
t
U
= 0.833ns
Example 7, F
NOM
= 200MHz
--
--
t
U
= 0.625ns
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
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INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
Skew (Pair #4)
LL
(1)
4t
U
Divide by 2
Divide by 2
LM
3t
U
6t
U
6t
U
LH
2t
U
4t
U
4t
U
ML
1t
U
2t
U
2t
U
M M
Zero Skew
Zero Skew
Zero Skew
M H
1t
U
2t
U
2t
U
HL
2t
U
4t
U
4t
U
H M
3t
U
6t
U
6t
U
H H
4t
U
Divide by 4
Inverted
(2)
NOTES:
1. LL disables outputs if TEST = MID and sOE = HIGH.
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
Description
Min.
Typ.
Max.
Unit
V
DD
/V
DDQ
Power Supply Voltage
3
3.3
3.6
V
T
A
Ambient Operating Temperature
-40
+25
+85
C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
--
0.8
V
V
IHH
Input HIGH Voltage
(1)
3-Level Inputs Only
V
DD
-
0.6
--
V
V
IMM
Input MID Voltage
(1)
3-Level Inputs Only
V
DD
/2
-
0.3
V
DD
/2+0.3
V
V
ILL
Input LOW Voltage
(1)
3-Level Inputs Only
--
0.6
V
I
IN
Input Leakage Current
V
IN
= V
DD
or GND
-
5
+5
A
(REF, FB Inputs Only)
V
DD
= Max.
V
IN
= V
DD
HIGH Level
--
+200
I
3
3-Level Input DC Current (TEST, FS, nF
[1:0]
)
V
IN
= V
DD
/2
MID Level
-
50
+50
A
V
IN
= GND
LOW Level
-
200
--
I
PU
Input Pull-Up Current (PE)
V
DD
= Max., V
IN
= GND
-
100
--
A
I
PD
Input Pull-Down Current (sOE)
V
DD
= Max., V
IN
= V
DD
--
+100
A
V
OH
Output HIGH Voltage
V
DDQ
= Min., I
OH
=
-
12mA
2.4
--
V
V
OL
Output LOW Voltage
V
DDQ
= Min., I
OL
= 12mA
--
0.4
V
NOTE:
1. These inputs are normally wired to V
DD
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DD
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(2)
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DD
= Max., TEST = MID, REF = LOW,
20
30
mA
PE = LOW, sOE = LOW, FS = MID
All outputs unloaded
I
DD
Power Supply Current per Input HIGH
V
IN
= 3V, V
DD
= Max., TEST = HIGH
1
30
A
(REF and FB inputs only)
FS = L
190
290
I
DDD
Dynamic Power Supply Current per Output
FS = M
150
230
A/MHz
FS = H
130
200
FS = L , F
VCO
= 50MHz, C
L
= 0pF
56
--
I
TOT
Total Power Supply Current
FS = M , F
VCO
= 100MHz, C
L
= 0pF
80
--
mA
FS = H, F
VCO
= 200MHz, C
L
= 0pF
125
--
NOTES:
1. Measurements are for divide-by-1 outputs and nF
[1:0]
= MM.
2. For nominal voltage and temperature.
INPUT TIMING REQUIREMENTS
Symbol
Description
(1)
Min.
Max.
Unit
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
--
10
ns/V
t
PWC
Input clock pulse, HIGH or LOW
2
--
ns
D
H
Input duty cycle
10
90
%
FS = LOW
6
50
F
REF
Reference clock input frequency
FS = MID
12
100
MHz
FS = HIGH
24
200
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
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