1
2000 Integrated Device Technology, Inc.
JANUARY 2001
DSC-4840/2
I/O
Control
Address
Decoder
128Kx9
MEMORY
ARRAY
7019
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/
W
L
A
16L
A
0L
I/O
0-8L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
R/
W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/
W
R
CE
0R
A
16R
A
0R
I/O
0-8R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/
S
(1)
CE
1L
R/
W
R
CE
0R
OE
R
CE
1R
4840 drw 01
1L
CE
1R
CE
17
17
Functional Block Diagram
x
M/
S = V
IH
for
BUSY output flag on Master,
M/
S = V
IL
for
BUSY input on Slave
x
Interrupt Flag
x
On-chip port arbitration logic
x
Full on-chip hardware support of semaphore signaling
between ports
x
Fully asynchronous operation from either port
x
TTL-compatible, single 5V (10%) power supply
x
Available in a 100-pin TQFP
x
Industrial temperature range (40C to +85C) is available
for selected speeds
Features
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
High-speed access
Commercial: 15/20ns (max.)
x
Low-power operation
IDT7019L
Active: 1W (typ.)
Standby: 1mW (typ.)
x
Dual chip enables allow for depth expansion without
external logic
x
IDT7019 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
HIGH-SPEED
128K x 9 DUAL-PORT
STATIC RAM
IDT7019L
NOTES:
1.
BUSY is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/
S = V
IH
).
2.
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
2
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Description
The IDT7019 is a high-speed 128K x 9 Dual-Port Static RAM. The
IDT7019 is designed to be used as a stand-alone 1152K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-
more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 18-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE
0
and CE
1
) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only1W of power.
The IDT7019 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Configurations
(1,2,3)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT7019PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
GND
OE
R
R/
W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
4840 drw 02
NC
NC
GND
OE
L
R/
W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
Vcc
A
15L
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
N
C
N
C
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
V
c
c
I
/
O
2
R
I
/
O
0
R
G
N
D
V
c
c
I
/
O
0
L
I
/
O
1
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
G
N
D
I
/
O
8
L
I
/
O
8
R
N
C
N
C
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
I
N
T
R
B
U
S
Y
R
M
/
S
B
U
S
Y
L
I
N
T
L
N
C
A
0
L
G
N
D
A
2
L
A
3
L
A
5
L
A
6
L
N
C
N
C
A
1
L
A
4
L
A
16L
A
16R
6.42
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Names
Left Port
Right Port
Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
16L
A
0R
- A
16R
Address
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power
GND
Ground
4840 tbl 01
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Capacitance
(T
A
= +25C, f = 1.0MHz)
Absolute Maximum Ratings
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
Recommended DC Operating
Conditions
NOTES:
1. Industrial Temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter T
A
. This is the "instant on" case temperature.
Maximum Operating Temperature
and Supply Voltage
(1)
Symbol
Rating
Commercial
& Industrial
Military
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
T
STG
Storage
Temperature
-65 to +150
-65 to +150
o
C
I
OUT
DC Output Current
50
50
mA
4840 tbl 02
Grade
Ambient
Temperature
(2)
GND
Vcc
Military
-55
O
C to +125
O
C
0V
5.0V
+
10%
Commercial
0
O
C to +70
O
C
0V
5.0V
+
10%
Industrial
-40
O
C to +85
O
C
0V
5.0V
+
10%
4840 tbl 03
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
(2)
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
4840 tbl 04
Symbol
Parameter
(1)
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
4840 tbl 05
4
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable
(1,2)
Truth Table II: Non-Contention Read/Write Control
NOTES:
1. A
0L
A
16L
A
0R
A
16R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from all the I/Os (I/O
0
-I/O
8
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or > V
CC
- 0.2V.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
CC
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
4840 tbl 06
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-8
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to memory
L
H
L
H
DATA
OUT
Read memory
X
X
H
X
High-Z
Outputs Disabled
4840 drw 07
Inputs
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-8
H
H
L
L
DATA
OUT
Read Semaphore Flag Data Out
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
______
Not Allowed
4840 tbl 08
6.42
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(2)
(V
CC
= 5.0V 10%)
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
Symbol
Parameter
Test Conditions
7019L
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
5
A
|I
LO
|
Output Leakage Current
CE = V
IH
, V
OUT
= 0V to V
CC
___
5
A
V
OL
Output Low Voltage
I
OL
= 4mA
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
V
4840 tbl 09
NOTES:
1. V
CC
= 5V, T
A
= +25C, and are not production tested. I
CCDC
= 120mA (Typ.)
2. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t
RC,
and using "AC Test Conditions" of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6,7)
(V
CC
= 5.0V 10%)
Symbol
Parameter
Test Condition
Version
7019L15
Com'l Only
Typ.
(1)
Max
7019L20
Com'l Only
Typ.
(1)
Max
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(2)
COM'L
L
220
340
200
300
mA
IND
L
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(2)
COM'L
L
65
100
50
75
mA
IND
L
____
____
____
____
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2)
,
SEM
R
=
SEM
L
= V
IH
COM'L
L
145
225
130
195
mA
IND
L
____
____
____
____
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V, V
IN
> V
CC
- 0.2V
or V
IN
< 0.2V, f = 0
(3)
SEM
R
=
SEM
L
> V
CC
- 0.2V
COM'L
L
0.2
3.0
0.2
3.0
mA
IND
L
____
____
____
____
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(4)
,
SEM
R
=
SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outputs Disabled , f = f
MAX
(2)
COM'L
L
135
220
120
190
mA
IND
L
____
____
____
____
4840 tbl 10
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