JANUARY 2001

DSC-4838/2

I/O

Control

Address
Decoder

32Kx18

MEMORY

ARRAY

7037

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

14L

SEM

INT

(2)

BUSY

(1,2)

I/O

Control

Address

Decoder

14R

SEM

INT

(2)

BUSY

(1,2)

(1)

4838 drw 01

I/O

9-17L

I/O

0-8R

I/O

9-17R

0-8L

Functional Block Diagram

S = V

for

BUSY output flag on Master,

S = V

for

BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling
between ports

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility

TTL-compatible, single 5V (±10%) power supply

Available in a 100-pin TQFP

Industrial temperature range (40°C to +85°C) is available
for selected speeds

Features

True Dual-Ported memory cells which allow simultaneous
reads of the same memory location

High-speed access
 Commercial: 15/20ns (max.)

Low-power operation
 IDT7037L

Active: 1W (typ.)
Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without
external logic

IDT7037 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device

HIGH-SPEED
32K x 18 DUAL-PORT
STATIC RAM

IDT7037L

NOTES:
1.

BUSY is an input as a Slave (M/S = V

) and an output when it is a Master (M/

S = V

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT7037 is a high-speed 32K x 18 Dual-Port Static RAM. The

IDT7037 is designed to be used as a stand-alone 576K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 36-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (

and CE

) permit the on-chip

circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these

devices typically operate on only 1W of power.

The IDT7037 is packaged in a 100-pin Thin Quad Flatpack (TQFP).

NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.

Pin Configurations

(1,2,3)

INDEX

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

SEM

12R

13R

11R

10R

14R

I
/
O

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

GND

4838 drw 02

I/O

15L

SEM

Vcc

GND

14L

13L

GND

12L

11L

10L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I
/
O

I
N

I
/
O

IDT7037PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

I/O

16R

I/O

17R

I/O

17L

I/O

16L

GND

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

, CE

Chip Enables

R/W

Read/Write Enable

Output Enable

- A

14L

- A

14R

Address

I/O

- I/O

17L

I/O

- I/O

17R

Data Input/Output

SEM

Semaphore Enable

Upper Byte Select

Lower Byte Select

INT

Interrupt Flag

BUSY

Busy Flag

M/S

Master or Slave Select

Power

GND

Ground

4838 tbl 01

NOTES:
1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

Capacitance

= +25°C, f = 1.0MHz)

Absolute Maximum Ratings

(1)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

2. V

TERM

must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> Vcc + 10%.

NOTES:
1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 10%.

Recommended DC Operating

Conditions

NOTES:
1. Industrial Temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T

. This is the "instant on" case temperature.

Maximum Operating Temperature

and Supply Voltage

(1)

Symbol

Rating

Commercial

& Industrial

Military

Unit

TERM

(2)

Terminal Voltage
with Respect
to GND

-0.5 to +7.0

BIAS

Temperature

Under Bias

-55 to +125

-65 to +135

STG

Storage

Temperature

-65 to +150

OUT

DC Output Current

4838 tbl 02

Grade

Ambient

Temperature

(2)

GND

Vcc

Military

-55

C to +125

5.0V

10%

Commercial

C to +70

5.0V

10%

Industrial

-40

C to +85

5.0V

10%

4838 tbl 03

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Ground

Input High Voltage

2.2

____

6.0

(2)

I L

Input Low Voltage

-0.5

(1)

____

0.8

4838 tbl 04

Symbol

Parameter

(1)

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

Output Capacitance

OUT

= 3dV

4838 tbl 05

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable

(1,2)

Truth Table II: Non-Contention Read/Write Control

NOTES:
1. A

14L

14R.

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control

(1)

NOTES:
1. There are eight semaphore flags written to via I/O

and read from all the I/Os (I/O

-I/O

). These eight semaphore flags are addressed by A

-A

2. Refer to Chip Enable Truth Table.

NOTES:
1. Chip Enable references are shown above with the actual

and CE

levels,

CE is a reference only.

2. 'H' = V

and 'L' = V

3. CMOS standby requires 'X' to be either < 0.2V or > V

- 0.2V.

Mode

Port Selected (TTL Active)

< 0.2V

-0.2V

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

-0.2V

Port Deselected (CMOS Inactive)

<0.2V

Port Deselected (CMOS Inactive)

4838 tbl 06

Inputs

(1)

Outputs

Mode

(2)

SEM

I/O

9-17

I/O

0-8

High-Z

Deselected: Power-Down

High-Z

Both Bytes Deselected

DATA

High-Z

Write to Upper Byte Only

High-Z

DATA

Write to Lower Byte Only

DATA

Write to Both Bytes

DATA

OUT

High-Z

Read Upper Byte Only

High-Z

DATA

OUT

Read Lower Byte Only

DATA

OUT

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

4838 tbl 07

Inputs

(1)

Outputs

Mode

(2)

SEM

I/O

9-17

I/O

0-8

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

Write I/O

into Semaphore Flag

DATA

Write I/O

into Semaphore Flag

______

Not Allowed

______

Not Allowed

4838 tbl 08

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(2)

= 5.0V ± 10%)

NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.

Symbol

Parameter

Test Conditions

7037L

Unit

Min.

Max.

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

___

µ A

Output Leakage Current

CE = V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= 4mA

___

0.4

Output High Voltage

= -4mA

2.4

___

4838 tbl 09

NOTES:
1. V

= 5V, T

= +25°C, and are not production tested. I

CCDC

= 120mA (Typ.)

2. At f = f

MAX

address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

RC,

and using "AC Test Conditions" of input levels

of GND to 3V.

3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1,6,7)

= 5.0V ± 10%)

Symbol

Parameter

Test Condition

Version

7037L15

Com'l Only

Typ.

(1)

Max

7037L20

Com'l Only

Typ.

(1)

Max

Unit

Dynamic Operating
Current
(Both Ports Active)

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(2)

COM'L

220

340

200

300

IND

____

SB1

Standby Current
(Both Ports - TTL Level
Inputs)

= V

SEM

= V

f = f

MAX

(2)

COM'L

100

IND

____

SB2

Standby Current
(One Port - TTL Level
Inputs)

"A"

= V

and

"B"

= V

(4)

Active Port Outputs Disabled,
f=f

MAX

(2)

SEM

= V

COM'L

145

225

130

195

IND

____

SB3

Full Standby Current
(Both Ports - All CMOS
Level Inputs)

Both Ports

and

> V

- 0.2V, V

> V

- 0.2V

or V

< 0.2V, f = 0

(3)

SEM

> V

- 0.2V

COM'L

0.2

3.0

0.2

3.0

IND

____

SB4

Full Standby Current
(One Port - All CMOS

Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(4)

SEM

> V

- 0.2V,

> V

- 0.2V or V

< 0.2V, Active Port

Outp uts Disabled, f = f

MAX

(2)

COM'L

135

220

120

190

IND

____

4838 tbl 10

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

Waveform of Read Cycles

(5)

NOTES:
1. Timing depends on which signal is asserted last,

OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first

CE, OE, LB or UB.

3. t

BDD

delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t

AOE

, t

ACE

, t

or t

BDD

SEM = V

6. Refer to Chip Enable Truth Table.

AC Test Conditions

Figure 2. Output Test Load

(for t

, t

)

* Including scope and jig.

Figure 1. AC Output Test Load

4838 drw 04

893

30pF

347

DATA

OUT

BUSY

INT

893

5pF*

347

DATA

OUT

4838 drw 03

ADDR

4838 drw 05

(4)

ACE

(4)

AOE

(4)

ABE

(4)

(1)

(2)

(3,4)

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

(6)

4838 drw 06

(6)

50%

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

Figures 1 and 2

4838 tbl 11

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage

(5)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM,

CE= V

and

SEM = V

. To access semaphore,

CE = V

and

SEM = V

. Either condition must be valid for the entire t

time.

4. The specification for t

must be met by the device supplying write data to the RAM under all operating conditions. Although t

and t

values will vary over voltage

and temperature, the actual t

will always be smaller than the actual t

5. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(5)

7037L15

Com'l Only

7037L20

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

____

Address Access Time

____

ACE

Chip Enable Access Time

(4)

____

ABE

Byte Enable Access Time

(4)

____

AOE

Output Enable Access Time

____

Output Hold from Address Change

____

Output Low-Z Time

(1,2)

____

Output High-Z Time

(1,2)

____

Chip Enable to Power Up Time

(2)

____

Chip Disable to Power Down Time

(2)

____

SOP

Semaphore Flag Update Pulse (

OE or SEM)

____

SAA

Semaphore Address Access Time

____

4838 tbl 12

Symbol

Parameter

7037L15

Com'l Only

7037L20

Com'l Only

Unit

Min.

Max.

Min.

Max.

WRITE CYCLE

Write Cycle Time

____

Chip Enable to End-of-Write

(3)

____

Address Valid to End-of-Write

____

Address Set-up Time

(3)

____

Write Pulse Width

____

Write Recovery Time

____

Data Valid to End-of-Write

____

Output High-Z Time

(1,2)

____

Data Hold Time

(4)

____

Write Enable to Output in High-Z

(1,2)

____

Output Active from End-of-Write

(1,2,4)

____

SWRD

SEM Flag Write to Read Time

____

SPS

SEM Flag Contention Window

____

4838 tbl 13

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

(1,5,8)

Timing Waveform of Write Cycle No. 2, CE Controlled Timing

(1,5)

NOTES:
1. R/

W or CE or UB and LB = V

during all address transitions.

2. A write occurs during the overlap (t

or t

) of a

CE = V

and a R/

W = V

for memory array writing cycle.

3. t

is measured from the earlier of

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the

CE or SEM = V

transition occurs simultaneously with or after the R/

W = V

transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If

OE = V

during R/W controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t

. If

OE = V

during an R/

W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified t

9. To access RAM,

CE = V

and

SEM = V

. To access semaphore,

CE = V

and

SEM = V

. t

must be met for either condition.

10. Refer to Chip Enable Truth Table.

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4)

(7)

4838 drw 07

(9)

SEM

(9,10)

(7)

(3)

4838 drw 08

ADDRESS

DATA

(3)

(2)

(6)

SEM

(9,10)

(9)

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side

(1)

NOTES:
1. D

= D

= V

or both

UB and LB = V

(Refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/

"A"

SEM

"A"

going HIGH to R/

"B"

SEM

"B"

going HIGH.

4. If t

SPS

is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

Timing Waveform of Semaphore Write Contention

(1,3,4)

NOTES:
1.

CE = V

UB and LB = V

for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

2. "DATA

OUT

VALID" represents all I/O's (I/O

- I/O

) equal to the semaphore value.

SEM

4838 drw 09

DATA

VALID ADDRESS

SAA

ACE

VALID ADDRESS

DATA

VALID

DATA

OUT

VALID

(2)

SWRD

AOE

SOP

Read Cycle

Write Cycle

-A

SOP

SEM

"A"

4838 drw 10

SPS

MATCH

"A"

MATCH

0"A"

-A

2"A"

SIDE

"A"

(2)

SEM

"B"

0"B"

-A

2"B"

SIDE

"B"

(2)

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

BUSY (M/S = V

)".

2. To ensure that the earlier of the two ports wins.
3. t

BDD

is a calculated parameter and is the greater of 0, t

WDD

(actual) or t

DDD

(actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(6)

7037L15

Com'l Only

7037L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S=V

)

BAA

BUSY Access Time from Address Match

____

BDA

BUSY Disable Time from Address Not Matched

____

BAC

BUSY Acce ss Time from Chip Enable Low

____

BDC

BUSY Acce ss Time from Chip Enable High

____

APS

Arbitration Priority Set-up Time

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

Write Hold After

BUSY

(5)

____

BUSY TIMING (M/S=V

)

BUSY Input to Write

(4)

____

Write Hold After

BUSY

(5)

____

PORT-TO-PORT DELAY TIMING

WDD

Write Pulse to Data Delay

(1)

____

DDD

Write Data Valid to Read Data Delay

(1)

____

4838 tbl 14

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing

(M/S = V

)

(1,3)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing

(M/S = V

)

(1)

NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If t

APS

is not satisfied, the

BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. Refer to Chip Enable Truth Table.

NOTES:
1. Industrial Temperature: for specific speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(1)

4838 drw 13

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"

"B"

BUSY

"B"

APS

BAC

BDC

(2)

4838 drw 14

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

7037L15

Com'l Only

7037L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

Address Set-up Time

____

Write Recovery Time

____

INS

Interrupt Set Time

____

INR

Interrupt Reset Time

____

4838 tbl 15

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

(1,5)

Truth Table IV Interrupt Flag

(1,4,5)

NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (

CE or R/W) is asserted last.

4. Timing depends on which enable signal (

or R/

W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

NOTES:
1. Assumes

BUSY

2. If

BUSY

= V

, then no change.

3. If

BUSY

= V

, then no change.

INT

and

INT

must be initialized at power-up.

5. Refer to Chip Enable Truth Table.

4838 drw 15

ADDR

"A"

INTERRUPT SET ADDRESS

"A"

(3)

(4)

INS

(3)

INT

"B"

(2)

4838 drw 16

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"

(3)

INR

(3)

INT

"B"

(2)

Left Port

Right Port

Function

R/W

14L

-A

INT

R/W

14R

-A

INT

7FFF

(2)

Set Right

INT

Flag

7FFF

)

Reset Right

INT

Flag

(3)

7FFE

Set Left

INT

Flag

7FFE

(2)

Reset Left

INT

Flag

4838 tbl 16

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT7037 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7037 has an automatic power down feature controlled
by

CE. The CE

and CE

control the on-chip power down circuitry that

permits the respective port to go into a standby mode when not selected
(

CE = HIGH). When a port is enabled, access to the entire memory array

is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(

INT

) is asserted when the right port writes to memory location 7FFE

(HEX), where a write is defined as

= R/

= V

per Truth Table

IV. The left port clears the interrupt through access of address location
7FFE when

= V

, R/

W is a "don't care". Likewise, the right

port interrupt flag (

INT

) is asserted when the left port writes to memory

location 7FFF (HEX) and to clear the interrupt flag (

INT

), the right port

must read the memory location 7FFF. The message (18 bits) at 7FFE or
7FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 7FFE and 7FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Table IV for the interrupt operation.

NOTES:
1. Pins

BUSY

and

BUSY

are both outputs when the part is configured as a master. Both are inputs when configured as a slave.

BUSY outputs on the IDT7037 are

push-pull, not open drain outputs. On slaves the

BUSY

input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t

APS

is not met, either

BUSY

= LOW will result.

BUSY

and

BUSY

outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when

BUSY

outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when

BUSY

outputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Chip Enable Truth Table.

NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7037.
2. There are eight semaphore flags written to via I/O

and read from all I/O's (I/O

-I/O

). These eight semaphores are addressed by A

-A

CE = V

SEM = V

to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table V Address BUSY

Arbitration

(4)

Truth Table VI Example of Semaphore Procurement Sequence

(1,2,3)

Inputs

Outputs

Function

-A

14L

-A

14R

BUSY

(1)

BUSY

(1)

NO MATCH

Normal

MATCH

Normal

MATCH

Normal

MATCH

(2)

Write

Inhibit

(3)

4838 tbl 17

Functions

- D

Left

- D

Right

Status

No Action

Semaphore free

Left Port Writes "0" to Semaphore

Left port has semaphore token

Right Port Writes "0" to Semaphore

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

Semaphore free

Right Port Writes "0" to Semaphore

Right port has semaphore token

Right Port Writes "1" to Semaphore

Semaphore free

Left Port Writes "0" to Semaphore

Left port has semaphore token

Left Port Writes "1" to Semaphore

Semaphore free

4838 tbl 18

6.42

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is "busy".
The

BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from
the side that receives a

BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of

BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the

BUSY outputs together

and use any

BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of

BUSY logic is

not desirable, the

BUSY logic can be disabled by placing the part in slave

mode with the M/

S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying
the

BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the

BUSY pin for that port LOW.

The

BUSY outputs on the IDT7037 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the

BUSY indication for the

resulting array requires the use of an external AND gate.

result in a glitched internal write inhibit signal and corrupted data in the
slave.

Semaphores

The IDT7037 is an extremely fast Dual-Port 32K x 18 CMOS Static

RAM with an additional 8 address locations dedicated to binary semaphore
flags. These flags allow either processor on the left or right side of the Dual-
Port RAM to claim a privilege over the other processor for functions defined
by the system designer's software. As an example, the semaphore can
be used by one processor to inhibit the other from accessing a portion of
the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by

CE, the Dual-Port RAM

enable, and

SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where

CE and SEM are both HIGH.

Systems which can best use the IDT7037 contain multiple

processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT7037s hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7037 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called "Token Passing Allocation." In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore's status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via

Width Expansion Busy Logic

Master/Slave Arrays

When expanding an IDT7037 RAM array in width while using

BUSY

logic, one master part is used to decide which side of the RAMs array will
receive a

BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use
the

BUSY signal as a write inhibit signal. Thus on the IDT7037 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = V

), and

the

BUSY pin is an input if the part used as a slave (M/S pin = V

) as shown

in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating

BUSY on one side of the

array and another master indicating

BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.

The

BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a

BUSY flag to be output from the master before the actual write

pulse can be initiated with the R/

W signal. Failure to observe this timing can

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7037 RAMs.

4838 drw 17

MASTER
Dual Port RAM

BUSY

MASTER
Dual Port RAM

SLAVE
Dual Port RAM

BUSY

IDT7037L
High-Speed 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.

The eight semaphore flags reside within the IDT7037 in a separate

memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the

SEM pin (which acts as a chip select for the

semaphore flags) and using the other control pins (Address,

CE, and

W) as they would be used in accessing a standard Static RAM. Each

of the flags has a unique address which can be accessed by either side
through address pins A

. When accessing the semaphores, none of

the other address pins has any effect.

When writing to a semaphore, only data pin D

is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side's output
register when that side's semaphore select (

SEM) and output enable (OE)

signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (

SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
VI). As an example, assume a processor writes a zero to the left port at
a free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right

side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side's semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip

Figure 4. IDT7037 Semaphore Logic

over to the other side as soon as a one is written into the first side's request
latch. The second side's flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.

4838 drw 18

WRITE

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

L PORT

R PORT

SEMAPHORE

READ

SEMAPHORE
READ

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