JULY 2002

DSC 5617/5

.unctional Block Diagram

.eatures:

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed data access
Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
6ns cycle time, 166MHz operation (12Gbps bandwidth)
Fast 3.6ns clock to data out
1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, 3.3V (±150mV) power supply
for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port

Industrial temperature range (-40°C to +85°C) is
available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70V3599/89S

REPEAT

16R

(1)

CNTEN

ADS

Dout0-8_R

Dout9-17_R

I/O

- I/O

35R

Din_R

ADDR_R

1/0

/PIPE

1a 0a

1b 0b

1c 0c

1d 0d

CLK

Counter/

Address

Reg.

d c b a

0/1

0d 1d

0c 1c

0b 1b

0a 1a

B
W
2
R

B
W
1
R

B
W
0
R

/PIPE

Counter/

Address

Reg.

CNTEN

ADS

REPEAT

Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L

Dout18-26_R
Dout27-35_R

B
W
0
L

B
W
1
L

B
W
2
L

B
W
3
L

I/O

- I/O

35L

16L

(1)

Din_L

ADDR_L

5617 tbl 01

128K x 36
MEMORY

ARRAY

CLK

a b c d

/PIPE

0/1

1d 0d

1c 0c

1b 0b 1a 0a

B
W
3
R

JTAG

TCK

TRST

TMS

TDO

TDI

1/0

0d 1d

0c 1c

0b 1b

0a 1a

/PIPE

1/0

NOTE:
1. A

is a NC for IDT70V3589.

6.42

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

IDT70V3599/89S

Description:

The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3599/89 has been optimized for applications having unidirectional

or bidirectional data flow in bursts. An automatic power down feature,
controlled by

and CE

permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70V3599/89 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V

) remains at 3.3V.

Pin Configuration

(1,2,3,4,5)

NOTES:

1. A

is a NC for IDT70V3589.

2. All V

pins must be connected to 3.3V power supply.

3. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

4. All V

pins must be connected to ground supply.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

A17

B17

I/O

15R

C17

D17

I/O

14R

E16

E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

B15

DDQR

C15

I/O

16R

D15

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

13L

14L

11L

15L

TDO

TDI

PL/

I/O

20L

I/O

18R

DDQR

I/O

21L

I/O

19R

18L

19L

I/O

20R

DDQL

I/O

22L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

28R

I/O

27R

I/O

29R

I/O

28L

DDQR

I/O

27L

DDQL

I/O

29L

I/O

30R

I/O

31L

I/O

31R

I/O

30L

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

33L

I/O

34R

TCK

I/O

33R

I/O

34L

DDQL

TMS

I/O

35L

PL/

TRST

11R

P12

CNTEN

U10

P10

T11

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

13R

U14

T14

R14

P14

I/O

P15

I/O

R15

DDQL

T15

I/O

U15

OPT

U16

I/O

U17

I/O

T16

T17

I/O

R17

DDQR

R16

I/O

P17

I/O

P16

N17

I/O

N16

I/O

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

I/O

M14

L17

I/O

L16

L15

I/O

L14

I/O

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

10R

H16

H15

H14

G17

I/O

11R

G16

I/O

10L

G15

DDQL

G14

I/O

F17

DDQR

F16

I/O

11L

F14

70V3599/89BF

BF-208

(6)

208-Pin fpBGA

Top View

(7)

F15

I/O

12R

R11

ADS

14R

16L

(1)

B10

C13

16R

(1)

R10

T10

10R

15R

5617 drw 02c

06/28/02

6.42

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

IDT70V3599/89S

Pin Configuration

(1,2,3,4,5)

(con't.)

NOTES:

1. A

is a NC for IDT70V3589.

2. All V

pins must be connected to 3.3V power supply.

3. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

4. All V

pins must be connected to ground supply.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

70V3599/89BC

BC-256

(6)

256-Pin BGA

Top View

(7)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

16L

(1)

PIPE/

TDO

I/O

20L

I/O

19R

I/O

19L

TDI

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L

I/O

22R

I/O

23R

DDQL

I/O

24R

I/O

24L

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L

I/O

28R

I/O

27R

DDQL

I/O

29R

I/O

29L

I/O

28L

DDQL

I/O

30L

I/O

31R

I/O

30R

DDQR

I/O

32R

I/O

32L

I/O

31L

DDQR

I/O

33L

I/O

34R

I/O

33R

PIPE/

I/O

35R

I/O

34L

TMS

16R

(1)

I/O

35L

TRST

TCK

13R

15R

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

I/O

P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R11

REPEAT

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5617 drw 02d

06/28/02

6.42

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

IDT70V3599/89S

Pin Configuration

(1,2,3,4,5)

(con't.)

NOTES:

1. A16 is a NC for IDT70V3589.

2. All V

pins must be connected to 3.3V power supply.

3. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

4. All V

pins must be connected to ground supply.

5. Package body is approximately 28mm x 28mm x 3.5mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

70V3599/89DR

DR-208

(6)

208-Pin PQFP

Top View

(7)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

I
/
O

(
1

)

I
/
O

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

I
/
O

(
1

)

I
/
O

5617 drw 02a

06/28/02

6.42

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

IDT70V3599/89S

Pin Names

Left Port

Right Port

Names

Chip Enables

(5)

R/W

Read/Write Enable

Output Enable

- A

16L

(1)

- A

16R

(1)

Address

I/O

- I/O

35L

I/O

- I/O

35R

Data Input/Output

CLK

Clock

PL/

Pipeline/Flow-Through

ADS

Address Strobe Enable

CNTEN

Counter Enable

REPEAT

Counter Repeat

(4)

Byte Enables (9-bit bytes)

(5)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(2)

OPT

Option for selecting V

DDQX

(2,3)

Power (3.3V)

(2)

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5617 tbl 01

NOTES:

1. A

is a NC for IDT70V3589.

2. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

3. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.

4. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

5. Chip Enables and Byte Enables are double buffered when PL/

FT = V

, i.e., the

signals take two cycles to deselect.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V3589

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V3589