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Электронный компонент: 70V7589

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2002 Integrated Device Technology, Inc.
DECEMBER 2002
DSC 5627/4
1
Functional Block Diagram
Features:
x
64K x 36 Synchronous Bank-Switchable Dual-ported SRAM
Architecture
64 independent 1K x 36 banks
2 megabits of memory on chip
x
Bank access controlled via bank address pins
x
High-speed data access
Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
x
Selectable Pipelined or Flow-Through output mode
x
Counter enable and repeat features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
5ns cycle time, 200MHz operation (14Gbps bandwidth)
Fast 3.4ns clock to data out
1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
x
Separate byte controls for multiplexed bus and bus
matching compatibility
x
LVTTL- compatible, 3.3V (150mV) power supply
for core
x
LVTTL compatible, selectable 3.3V (150mV) or 2.5V
(100mV) power supply for I/Os and control signals on
each port
x
Industrial temperature range (-40C to +85C) is
available at 166MHz and 133MHz
x
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
x
Supports JTAG features compliant with IEEE 1149.1
HIGH-SPEED 3.3V 64K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7589S
1Kx36
MEMORY
ARRAY
(BANK 63)
MUX
MUX
PL/
FT
L
OPT
L
CLK
L
ADS
L
CNTEN
L
REPEAT
L
R/
W
L
CE
0L
CE
1L
BE
3L
BE
2L
BE
1L
BE
0L
OE
L
I/O
0L-35L
A
9L
A
0L
JTAG
1Kx36
MEMORY
ARRAY
(BANK 1)
MUX
MUX
1Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
I/O
0R-35R
A
9R
A
0R
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
5627 drw 01
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
,
PL/
FT
R
OPT
R
CLK
R
ADS
R
CNTEN
R
REPEAT
R
R/
W
R
CE
0R
CE
1R
BE
3R
BE
2R
BE
1R
BE
0R
OE
R
TMS
TCK
TRST
TDI
TDO
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
6.42
2
IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Description:
The IDT70V7589 is a high-speed 64Kx36 (2Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
1Kx36 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 1Kx36 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
Pin Configuration
(1,2,3,4)
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
A17
V
SS
B17
I/O
15R
C17
V
SS
D17
I/O
14R
E16
V
SS
E17
I/O
13L
D16
I/O
14L
C16
I/O
15L
B16
I/O
16L
A16
I/O
17L
A15
OPT
L
B15
V
DDQR
C15
I/O
16R
D15
V
DDQL
E15
I/O
13R
E14
I/O
12L
D14
I/O
17R
D13
V
DD
C12
A
6L
C14
V
DD
B14
V
SS
A14
A
0L
A12
CNTEN
L
B12
A
5L
C11
R/
W
L
D12
A
3L
D11
REPEAT
L
C10
V
SS
B11
ADS
L
A11
CLK
L
D8
BE
0L
C8
BE
3L
A9
BE
1L
D9
V
DD
C9
CE
1L
B9
CE
0L
D10
OE
L
C7
BA
0L
B8
BE
2L
A8
A
8L
B13
A
1L
A13
A
4L
A10
V
DD
D7
A
7L
B7
A
9L
A7
BA
2L
B6
BA
3L
C6
BA
4L
D6
BA
1L
A5
NC
B5
NC
C5
NC
D5
BA
5L
A4
TDO
B4
TDI
C4
PL/
FT
L
D4
I/O
20L
A3
V
SS
B3
I/O
18R
C3
V
DDQR
D3
I/O
21L
D2
V
SS
C2
I/O
19R
B2
V
SS
A2
I/O
18L
A1
I/O
19L
B1
I/O
20R
C1
V
DDQL
D1
I/O
22L
E1
I/O
23L
E2
I/O
22R
E3
V
DDQR
E4
I/O
21R
F1
V
DDQL
F2
I/O
23R
F3
I/O
24L
F4
V
SS
G1
I/O
26L
G2
V
SS
G3
I/O
25L
G4
I/O
24R
H1
V
DD
H2
I/O
26R
H3
V
DDQR
H4
I/O
25R
J1
V
DDQL
J2
V
DD
J3
V
SS
J4
V
SS
K1
I/O
28R
K2
V
SS
K3
I/O
27R
K4
V
SS
L1
I/O
29R
L2
I/O
28L
L3
V
DDQR
L4
I/O
27L
M1
V
DDQL
M2
I/O
29L
M3
I/O
30R
M4
V
SS
N1
I/O
31L
N2
V
SS
N3
I/O
31R
N4
I/O
30L
P1
I/O
32R
P2
I/O
32L
P3
V
DDQR
P4
I/O
35R
R1
V
SS
R2
I/O
33L
R3
I/O
34R
R4
TCK
T1
I/O
33R
T2
I/O
34L
T3
V
DDQL
T4
TMS
U1
V
SS
U2
I/O
35L
U3
PL/
FT
R
U4
NC
P5
TRST
R5
NC
U6
BA
1R
P12
CNTEN
R
P8
A
8R
U10
OE
R
P9
BE
1R
R8
BE
2R
T8
BE
3R
U9
V
DD
P10
V
DD
T11
R/
W
R
U8
BE
0R
P11
CLK
R
R12
A
5R
T12
A
6R
U12
A
3R
P13
A
4R
P7
BA
2R
R13
A
1R
T13
A
2R
U13
A
0R
R6
BA
3R
T5
NC
U7
A
7R
U14
V
DD
T14
V
SS
R14
V
SS
P14
I/O
2L
P15
I/O
3L
R15
V
DDQL
T15
I/O
0R
U15
OPT
R
U16
I/O
0L
U17
I/O
1L
T16
V
SS
T17
I/O
2R
R17
V
DDQR
R16
I/O
1R
P17
I/O
4L
P16
V
SS
N17
I/O
5L
N16
I/O
4R
N15
V
DDQL
N14
I/O
3R
M17
V
DDQR
M16
I/O
5R
M15
I/O
6L
M14
V
SS
L17
I/O
8L
L16
V
SS
L15
I/O
7L
L14
I/O
6R
K17
V
SS
K16
I/O
8R
K15
V
DDQL
K14
I/O
7R
J17
V
DDQR
J16
V
SS
J15
V
DD
J14
V
SS
H17
I/O
10R
H16
V
SS
H15
IO
9R
H14
V
DD
G17
I/O
11R
G16
I/O
10L
G15
V
DDQL
G14
I/O
9L
F17
V
DDQR
F16
I/O
11L
F14
V
SS
70V7589BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
F15
I/O
12R
R9
CE
0R
R11
ADS
R
T6
BA
4R
T9
CE
1R
A6
NC
B10
V
SS
C13
A
2L
P6
NC
R10
V
SS
R7
A
9R
T10
V
SS
T7
BA
0R
U5
BA
5R
5627 drw 02c
,
11/08/01
register, the IDT70V7589 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE
0
and CE
1
, permits the on-chip circuitry of each
port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.
The 70V7589 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(V
DD
) remains at 3.3V. Please refer also to the
functional description on page 19.
6.42
IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Configuration
(1,2,3,4)
(con't.)
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
70V7589BC
BC-256
(5)
256-Pin BGA
Top View
(6)
E16
I/O
14R
D16
I/O
16R
C16
I/O
16L
B16
NC
A16
NC
A15
NC
B15
I/O
17L
C15
I/O
17R
D15
I/O
15L
E15
I/O
14L
E14
I/O
13L
D14
I/O
15R
D13
V
DD
C12
A
6L
C14
OPT
L
B14
V
DD
A14
A
0L
A12
A
5L
B12
A
4L
C11
ADS
L
D12
V
DDQR
D11
V
DDQR
C10
CLK
L
B11
REPEAT
L
A11
CNTEN
L
D8
V
DDQR
C8
BE
1L
A9
CE
1L
D9
V
DDQL
C9
BE
0L
B9
CE
0L
D10
V
DDQL
C7
A
7L
B8
BE
3L
A8
BE
2L
B13
A
1L
A13
A
2L
A10
OE
L
D7
V
DDQR
B7
A
9L
A7
A
8L
B6
BA
2L
C6
BA
0L
D6
V
DDQL
A5
BA
4L
B5
BA
5L
C5
BA
3L
D5
V
DDQL
A4
NC
B4
NC
C4
NC
D4
PL/
FT
L
A3
NC
B3
TDO
C3
V
SS
D3
I/O
20L
D2
I/O
19R
C2
I/O
19L
B2
NC
A2
TDI
A1
NC
B1
I/O
18L
C1
I/O
18R
D1
I/O
20R
E1
I/O
21R
E2
I/O
21L
E3
I/O
22L
E4
V
DDQL
F1
I/O
23L
F2
I/O
22R
F3
I/O
23R
F4
V
DDQL
G1
I/O
24R
G2
I/O
24L
G3
I/O
25L
G4
V
DDQR
H1
I/O
26L
H2
I/O
25R
H3
I/O
26R
H4
V
DDQR
J1
I/O
27L
J2
I/O
28R
J3
I/O
27R
J4
V
DDQL
K1
I/O
29R
K2
I/O
29L
K3
I/O
28L
K4
V
DDQL
L1
I/O
30L
L2
I/O
31R
L3
I/O
30R
L4
V
DDQR
M1
I/O
32R
M2
I/O
32L
M3
I/O
31L
M4
V
DDQR
N1
I/O
33L
N2
I/O
34R
N3
I/O
33R
N4
PL/
FT
R
P1
I/O
35R
P2
I/O
34L
P3
TMS
P4
NC
R1
I/O
35L
R2
NC
R3
TRST
R4
NC
T1
NC
T2
TCK
T3
NC
T4
NC
P5
BA
3R
R5
BA
5R
P12
A
6R
P8
BE
1R
P9
BE
0R
R8
BE
3R
T8
BE
2R
P10
CLK
R
T11
CNTEN
R
P11
ADS
R
R12
A
4R
T12
A
5R
P13
A
3R
P7
A
7R
R13
A
1R
T13
A
2R
R6
BA
2R
T5
BA
4R
T14
A
0R
R14
OPT
R
P14
I/O
0L
P15
I/O
0R
R15
NC
T15
NC
T16
NC
R16
NC
P16
I/O
1L
N16
I/O
2R
N15
I/O
1R
N14
I/O
2L
M16
I/O
4L
M15
I/O
3L
M14
I/O
3R
L16
I/O
5R
L15
I/O
4R
L14
I/O
5L
K16
I/O
7L
K15
I/O
6L
K14
I/O
6R
J16
I/O
8L
J15
I/O
7R
J14
I/O
8R
H16
I/O
10R
H15
IO
9L
H14
I/O
9R
G16
I/O
11R
G15
I/O
11L
G14
I/O
10L
F16
I/O
12L
F14
I/O
12R
F15
I/O
13R
R9
CE
0R
R11
REPEAT
R
T6
BA
1R
T9
CE
1R
A6
BA
1L
B10
R/
W
L
C13
A
3L
P6
BA
0R
R10
R/
W
R
R7
A
9R
T10
OE
R
T7
A
8R
,
E5
V
DD
E6
V
DD
E7
V
SS
E8
V
SS
E9
V
SS
E10
V
SS
E11
V
DD
E12
V
DD
E13
V
DDQR
F5
V
DD
F6
V
SS
F8
V
SS
F9
V
SS
F10
V
SS
F12
V
DD
F13
V
DDQR
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
SS
G12
V
SS
G13
V
DDQL
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
SS
H13
V
DDQL
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
SS
J13
V
DDQR
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
L5
V
DD
L6
V
SS
L7
V
SS
L8
V
SS
M5
V
DD
M6
V
DD
M7
V
SS
M8
V
SS
N5
V
DDQR
N6
V
DDQR
N7
V
DDQL
N8
V
DDQL
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DD
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DD
N9
V
DDQR
N10
V
DDQR
N11
V
DDQL
N12
V
DDQL
K13
V
DDQR
L13
V
DDQL
M13
V
DDQL
N13
V
DD
F7
V
SS
F11
V
SS
5627 drw 02d
,
11/08/01
6.42
4
IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
70V7589DR
DR-208
(5)
208-Pin PQFP
Top View
(6)
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SS
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SS
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SS
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SS
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SS
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SS
I/O
33R
I/O
33L
I/O
34R
I/O
34L
V
S
S
V
D
D
Q
L
I/O
3
5R
I/O
3
5L
P
L/
F
T
R
T
M
S
T
C
K
T
R
S
T
N
C
N
C
N
C
N
C
B
A
5R
B
A
4R
B
A
3R
B
A
2R
B
A
1R
B
A
0R
A
9R
A
8R
A
7R
B
E
3R
B
E
2R
B
E
1R
B
E
0R
C
E
1R
C
E
0R
V
D
D
V
D
D
V
S
S
V
S
S
C
LK
R
O
E
R
R
/
W
R
A
D
S
R
C
N
T
E
N
R
R
E
P
E
A
T
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
D
D
V
S
S
V
S
S
O
P
T
R
I/O
0L
I/O
0R
V
D
D
Q
L
V
S
S
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SS
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SS
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SS
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
V
S
S
V
D
D
Q
R
I/O
18
R
I/O
18
L
V
S
S
P
L
/
F
T
L
T
D
I
T
D
O
N
C
N
C
N
C
N
C
B
A
5L
B
A
4L
B
A
3L
B
A
2L
B
A
1L
B
A
0L
A
9
L
A
8
L
A
7
L
B
E
3L
B
E
2L
B
E
1L
B
E
0L
C
E
1L
C
E
0L
V
D
D
V
D
D
V
S
S
V
S
S
C
LK
L
O
E
L
R
/
W
L
A
D
S
L
C
N
T
E
N
L
R
E
P
E
A
T
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
V
D
D
V
D
D
V
S
S
O
P
T
L
I/O
17
L
I/O
17
R
V
D
D
Q
R
V
S
S
5627 drw 02a
,
11/08/01
6.42
IDT70V7589S
High-Speed 64K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
Pin Names
Left Port
Right Port
Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
BA
0L
- BA
5L
BA
0R
- BA
5R
Bank Address
(4)
A
0L
- A
9L
A
0R
- A
9R
Address
I/O
0L
- I/O
35L
I/O
0R
- I/O
35R
Data Input/Output
CLK
L
CLK
R
Clock
PL/
FT
L
PL/
FT
R
Pipeline/Flow-Through
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
REPEAT
L
REPEAT
R
Counter Repeat
(3)
BE
0L
-
BE
3L
BE
0R
-
BE
3R
Byte Enables (9-bit bytes)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(1)
OPT
L
OPT
R
Option for selecting V
DDQX
(1,2)
V
DD
Power (3.3V)
(1)
V
SS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5627 tbl 01
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA
0L
- BA
5L
BA
0R
- BA
5R
). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).