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Электронный компонент: 70V9289

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2003 Integrated Device Technology, Inc.
APRIL 2003
DSC-4856/3
1
Functional Block Diagram
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial: 6/7.5/9/12ns (max.)
Industrial: 9ns (max.)
Low-power operation
IDT70V9389/289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (0.3V) power supply
Industrial temperature range (40C to +85C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) and
100-pin Thin Quad Flatpack (TQFP)
IDT70V9389/289L
0a 1a
0b 1b
0/1
a
b
I/O
Control
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
MEMORY
ARRAY
Counter/
Address
Reg.
4856 drw 01
A
15R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
9L
-I/O
17L
(2)
I/O
0L
-I/O
8L
(1)
I/O
9R
-I/O
17R
(1)
I/O
0R
-I/O
8R
(1)
A
15L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
1
0/1
0
1b 0b
1a 0a
0/1
b a
I/O
Control
FT
/PIPE
L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
HIGH-SPEED 3.3V
64K x18/x16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
NOTE:
1. I/O
0X
- I/O
7X
for IDT70V9289.
2. I/O
8X
- I/O
15X
for IDT70V9289.
6.42
2
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
NC
NC
NC
NC
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
NC
CNTEN
R
CLK
R
ADS
R
V
SS
V
DD
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
NC
NC
NC
NC
I/O
12L
I/O
11L
V
DD
NC
I/O
10L
I/O
9L
I/O
8L
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
V
SS
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
V
DD
V
SS
I/O
0R
I/O
2R
I/O
1R
V
SS
I/O
4R
I/O
5R
I/O
6R
V
DD
I/O
7R
I/O
8R
I/O
9R
I/O
10R
NC
V
SS
I/O
11R
I/O
12R
V
DD
I/O
3R
70V9389PRF
PK-128-1
(4)
128-Pin TQFP
Top View
(5)
4856 drw 02
A
1
0
R
A
1
1
R
A
1
2
R
A
1
3
R
A
1
4
R
A
1
5
R
N
C
N
C
L
B
R
U
B
R
C
E
0
R
C
E
1
R
C
N
T
R
S
T
R
V
D
D
V
S
S
R
/
W
R
O
E
R
F
T
/
P
I
P
E
R
V
S
S
I
/
O
1
7
R
I
/
O
1
6
R
I
/
O
1
5
R
I
/
O
1
4
R
V
D
D
V
D
D
I
/
O
1
3
R
A
1
0
L
A
1
1
L
A
1
2
L
A
1
3
L
A
1
4
L
A
1
5
L
N
C
N
C
L
B
L
U
B
L
C
E
0
L
C
E
1
L
C
N
T
R
S
T
L
V
D
D
V
S
S
R
/
W
L
O
E
L
F
T
/
P
I
P
E
L
V
S
S
I
/
O
1
7
L
I
/
O
1
6
L
I
/
O
1
5
L
I
/
O
1
4
L
V
D
D
V
S
S
I
/
O
1
3
L
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
CNTEN
L
CLK
L
ADS
L
03/28/03
Description:
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Pin Configuration
(1,2,3)
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9389/289 has been optimized
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 500mW of power.
6.42
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
3
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
FT
/PIPE
R
OE
R
R/
W
R
CNTRST
R
CE
1R
CE
0R
V
SS
A
12R
A
13R
A
11R
A
10R
A
9R
A
14R
I
/
O
1
0
R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
V
SS
UB
R
LB
R
4856 drw 02a
I/O
15L
FT
/PIPE
L
OE
L
R/
W
L
CNTRST
L
CE
1L
CE
0L
V
DD
A
14L
A
13L
A
12L
A
11L
A
10L
A
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
V
SS
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
V
S
S
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
I
/
O
8
R
I
/
O
9
R
I
/
O
8
L
I
/
O
9
L
I
/
O
6
R
A
7
R
A
8
L
A
7
L
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
L
K
R
C
N
T
E
N
R
C
L
K
L
C
N
T
E
N
L
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
A
8R
V
S
S
V
D
D
I
/
O
1
L
V
D
D
V
S
S
70V9389PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
A
15R
A
15L
I/O
16R
I/O
17R
I/O
17L
I/O
16L
A
D
S
L
A
D
S
R
V
S
S
,
03/28/03
Pin Configurations
(1,2,3)
(con't.)
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
4
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
NC
NC
NC
NC
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
NC
CNTEN
R
CLK
R
ADS
R
V
SS
V
DD
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
NC
NC
NC
NC
I/O
10L
I/O
9L
V
DD
NC
I/O
8L
NC
NC
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
V
SS
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
V
DD
V
SS
I/O
0R
I/O
2R
I/O
1R
V
SS
I/O
4R
I/O
5R
I/O
6R
V
DD
I/O
7R
NC
NC
I/O
8R
NC
V
SS
I/O
9R
I/O
10R
I/O
3R
70V9289PRF
PK-128-1
(4)
128-Pin TQFP
Top View
(5)
4856 drw 02b
A
1
0
R
A
1
1
R
A
1
2
R
A
1
3
R
A
1
4
R
A
1
5
R
N
C
N
C
L
B
R
U
B
R
C
E
0
R
C
E
1
R
C
N
T
R
S
T
R
V
D
D
V
S
S
R
/
W
R
O
E
R
F
T
/
P
I
P
E
R
V
S
S
I
/
O
1
5
R
I
/
O
1
4
R
I
/
O
1
3
R
I
/
O
1
2
R
V
D
D
V
D
D
I
/
O
1
1
R
A
1
0
L
A
1
1
L
A
1
2
L
A
1
3
L
A
1
4
L
A
1
5
L
N
C
N
C
L
B
L
U
B
L
C
E
0
L
C
E
1
L
C
N
T
R
S
T
L
V
D
D
V
S
S
R
/
W
L
O
E
L
F
T
/
P
I
P
E
L
V
S
S
I
/
O
1
5
L
I
/
O
1
4
L
I
/
O
1
3
L
I
/
O
1
2
L
V
D
D
V
S
S
I
/
O
1
1
L
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
CNTEN
L
CLK
L
ADS
L
V
DD
03/28/03
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges
5
Pin Configurations
(1,2,3)
(con't.)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V9289PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
4856 drw 02c
I/O
15L
OE
L
R/
W
L
CNTRST
L
CE
1L
CE
0L
V
DD
NC
A
14L
A
13L
NC
A
12L
A
11L
A
10L
A
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
V
SS
I
/
O
6
R
I
/
O
5
R
FT
/PIPE
R
OE
R
R/
W
R
CNTRST
R
CE
1R
CE
0R
NC
NC
V
SS
A
12R
A
13R
A
11R
A
10R
A
9R
A
14R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
V
SS
UB
R
LB
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
I
/
O
I
L
V
S
S
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
N
C
I
/
O
8
R
I
/
O
9
R
I
/
O
8
L
I
/
O
9
L
FT
/PIPE
L
A
8
R
A
7
R
A
8
L
A
7
L
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
N
T
E
N
R
C
L
K
R
A
D
S
R
A
D
S
L
C
L
K
L
C
N
T
E
N
L
A
0
L
V
S
S
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
V
S
S
V
D
D
V
D
D
A
15L
A
15R
.
03/28/03
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.