FEBRUARY 2001
DSC-2964/14
1
2000 Integrated Device Technology, Inc.
Features
x
x
x
x
x
128K x 8 advanced high-speed CMOS static RAM
x
x
x
x
x
Commercial (0C to +70C), Industrial (40C to +85C)
x
x
x
x
x
Equal access and cycle times
-- Commercial and Industrial: 12/15/20ns
x
x
x
x
x
Two Chip Selects plus one Output Enable pin
x
x
x
x
x
Bidirectional inputs and outputs directly
TTL-compatible
x
x
x
x
x
Low power consumption via chip deselect
x
x
x
x
x
Available in 300 and 400 mil Plastic SOJ.
Functional Block Diagram
Description
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71024 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71024 are TTL-compat-
ible, and operation is from a single 5V supply. Fully static asynchro-
nous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-
pin 400 mil Plastic SOJ.
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
16
2964 drw 01
8
8
I/O
0
I/O
7
8
CONTROL
LOGIC
WE
OE
CS
1
CS
2
CMOS Static RAM
1 Meg (128K x 8-Bit)
IDT71024
6.42
2
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Truth Table
(1,2)
Absolute Maximum Ratings
(1)
Pin Configuration
SOJ
Top View
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
5
6
7
8
9
10
11
12
NC
A
16
A
14
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
12
A
7
A
6
A
5
A
4
CS
2
A
13
A
8
A
9
A
11
WE
A
10
2964 drw 02
A
3
13
20
OE
14
19
15
18
16
GND
17
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
CS
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
SO32-2
SO32-3
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
0.2V.
3. Other inputs
V
HC
or
V
LC.
Inputs
I/O
Function
WE
CS
1
CS
2
OE
X
H
X
X
High-Z
Deselected Standby (I
SB
)
X
V
HC
(3)
X
X
High-Z
Deselected Standby (I
SB1
)
X
X
L
X
High-Z
Deselected Standby (I
SB
)
X
X
V
LC
(3)
X
High-Z
Deselected Standby (I
SB1
)
H
L
H
H
High-Z
Outputs Disabled
H
L
H
L
DATA
OUT
Read Data
L
L
H
X
DATA
IN
Write Data
2964 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
Symbol
Rating
Value
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
o
C
T
STG
Storage Temperature
55 to +125
o
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
2964 tbl 02
Grade
Temperature
GND
V
CC
Commercial
0C to +70C
0V
5.0V 0.5V
Industrial
40C to +85C
0V
5.0V 0.5V
2964 tbl 05
NOTE:
1. V
IL
(min.) = 1.5V for pulse width less than 10ns, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
V
CC
+0.5
V
V
IL
Input Low Voltage
0.5
(1)
____
0.8
V
2964 tbl 04
Capacitance
(T
A
= +25C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
2964 tbl 03
6.42
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
3
DC Electrical Characteristics
(1)
(V
CC
= 5.0V 10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
DC Electrical Characteristics
(V
CC
= 5.0V 10%, Commercial and Industrial Temperature Ranges)
Symbol
Parameter
Test Condition
IDT71024
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
___
5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS
1
= V
IH
, V
OUT
= GND to V
CC
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= 4mA, V
CC
= Min.
2.4
___
V
2964 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
71024S12
71024S15
71024S20
Symbol
Parameters
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
I
CC
Dynamic Operating Current,
CS
2
V
IH
and
CS
1
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
160
160
155
155
140
140
mA
I
SB
Standby Power Supply Current (TTL Level)
CS
1
V
IH
or CS
2
V
IL
, Outputs Open,
V
CC
= Max., f=f
MAX
(2)
40
40
40
40
40
40
mA
I
SB1
Full Standby Power Supply Current
(CMOS Level),
CS
1
V
HC
or
CS
2
V
LC
, Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
V
LC
or V
IN
V
HC
10
10
10
10
10
10
mA
2964 tbl 07
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
*Including jig and scope capacitance.
2964 drw 03
480
255
30pF
DATA
OUT
5V
2964 drw 04
480
255
5pF*
DATA
OUT
5V
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2964 tbl 08
AC Test Conditions
6.42
4
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V 10%, Commercial and Industrial Temperature Ranges)
71024S12
71024S15
71024S20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
12
--
15
--
20
--
ns
t
AA
Address Access Time
--
12
--
15
--
20
ns
t
ACS
Chip Select Access Time
--
12
--
15
--
20
ns
t
CLZ
(1)
Chip Sele ct to Output in Low-Z
3
--
3
--
3
--
ns
t
CHZ
(1)
Chip Desele ct to Output in High-Z
0
6
0
7
0
8
ns
t
OE
Output Enable to Output Valid
--
6
--
7
--
8
ns
t
OLZ
(1)
Output Enab le to Output in Low-Z
0
--
0
--
0
--
ns
t
OHZ
(1)
Output Disable to Output in High-Z
0
5
0
5
0
7
ns
t
OH
Output Hold from Address Change
4
--
4
--
4
--
ns
t
PU
(1)
Chip Select to Power-Up Time
0
--
0
--
0
--
ns
t
PD
(1)
Chip Deselect to Power-Down Time
--
12
--
15
--
20
ns
Write Cycle
t
WC
Write Cycle Time
12
--
15
--
20
--
ns
t
AW
Address Valid to End-of-Write
10
--
12
--
15
--
ns
t
CW
Chip Select to End-of-Write
10
--
12
--
15
--
ns
t
AS
Address Set-Up Time
0
--
0
--
0
--
ns
t
WP
Write Pulse Width
8
--
12
--
15
--
ns
t
WR
Write Recovery Time
0
--
0
--
0
--
ns
t
DW
Data Valid to End-of-Write
7
--
8
--
9
--
ns
t
DH
Data Hold Time
0
--
0
--
0
--
ns
t
OW
(1)
Output Active from End-of-Write
3
--
3
--
4
--
ns
t
WHZ
(1)
Write Enab le to Output in High-Z
0
5
0
5
0
8
ns
2964 tbl 09
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
5
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS
1
is LOW, CS
2
is HIGH.
3. Address must be valid prior to or coincident with the later of
CS
1
transition LOW and CS
2
transition HIGH; otherwise t
AA
is the limiting parameter.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
ADDRESS
2964 drw 05
OE
CS
1
(5)
(5)
(5)
(5)
CS
2
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
DATA
OUT
t
PU
t
PD
Vcc
SUPPLY
CURRENT
Icc
I
SB
DATA
OUT
ADDRESS
2964 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
PDF 
ZIP