FEBRUARY 2001
DSC-3514/10
1
2000 Integrated Device Technology, Inc.
Features
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x
x
x
x
128K x 8 advanced high-speed CMOS static RAM
x
x
x
x
x
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
x
x
x
x
x
Equal access and cycle times
Commercial and Industrial: 12/15/20ns
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x
x
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x
One Chip Select plus one Output Enable pin
x
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Bidirectional inputs and outputs directly TTL-compatible
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x
Low power consumption via chip deselect
x
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x
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x
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
Description
The IDT71124 is a 1,048,576-bit high-speed static RAM orga-
nized as 128K x 8. It is fabricated using IDT's high-performance,
high-reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs. The JEDEC
centerpower/GND pinout reduces noise generation and improves
system performance.
The IDT71124 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71124 are TTL-compatible
and operation is from a single 5V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
16
3514 drw 01
8
8
I/O
0
- I/O
7
8
CONTROL
LOGIC
WE
OE
CS
,
CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
IDT71124
6.42
2
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
Capacitance
(T
A
= +25C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
8
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
3514 tbl 03
Recommended DC Operating
Conditions
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
V
CC
+0.5
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
3514 tbl 05
Grade
Temperature
GND
V
CC
Commercial
0C to +70C
0V
5.0V 10%
Industrial
40C to +85C
0V
5.0V 10%
3514 tbl 04
Recommended Operating
Temperature and Supply Voltage
Pin Configuration
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliabilty.
2. V
TERM
must not exceed Vcc + 0.5V.
Truth Table
(1,2)
SOJ
Top View
5
6
7
8
9
10
11
12
A
0
A
1
A
2
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
3
CS
I/O
1
V
CC
A
14
OE
I/O
7
I/O
6
GND
I/O
5
3514 drw 02
GND
13
20
14
19
15
18
16
A
7
17
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
12
A
11
A
10
A
9
A
8
SO32-3
I/O
0
A
16
A
13
V
CC
I/O
4
,
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs
VHC or
VLC.
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected - Standby (I
SB
)
V
HC
(3)
X
X
High-Z
Deselected - Standby (I
SB1
)
3514 tbl 01
Absolute Maximum Ratings
(1)
Symbol
Rating
Value
Unit
V
TERM
(2)
Terminal Voltage with
Respect to GND
-0.5 to +7.0
(2)
V
T
A
Operating Temperature
0 to +70
o
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
3514 tbl 02
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
3
3514 drw 03
480
255
30pF
DATA
OUT
5V
.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 1. AC Test Load
AC Test Conditions
DC Electrical Characteristics
(1)
(V
CC
= 5.0V 10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
3514 drw 04
480
255
5pF*
DATA
OUT
5V
.
DC Electrical Characteristics
(V
CC
= 5.0V 10%, Commercial and Industrial Temperature Ranges)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
___
5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= GND to V
CC
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= 4mA, V
CC
= Min.
2.4
___
V
3514 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
71124S12
71124S15
71124S20
Symbol
Parameter
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
I
CC
Dynamic Operating Current
CS < V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
160
160
155
155
140
140
mA
I
SB
Standby Power Supply Current (TTL Level)
CS > V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
40
40
40
40
40
40
mA
I
SB1
Full Standby Power Supply Current (CMOS Level)
CS > V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
V
IN
< V
LC
or V
IN
> V
HC
10
10
10
10
10
10
mA
3514 tbl 07
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3514 tbl 08
AC Test Loads
6.42
4
IDT71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V 10%, Commercial and Industrial Temperature Ranges)
71124S12
71124S15
71124S20
Sym bol
Param eter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Re ad Cyc le Tim e
12
____
15
____
20
____
ns
t
AA
A d d re ss A cc e ss Tim e
____
12
____
15
____
20
ns
t
ACS
Chip S e le ct A cc e ss Tim e
____
12
____
15
____
20
ns
t
CLZ
(1)
Chip Se le c t to Outp ut in Lo w-Z
3
____
3
____
3
____
ns
t
CHZ
(1)
Chip De se le c t to Outp ut in Hig h-Z
0
6
0
7
0
8
ns
t
OE
Outp ut E nab le to Outp ut Valid
____
6
____
7
____
8
ns
t
OLZ
(1)
Outp ut E nab l e to Outp ut in Lo w-Z
0
____
0
____
0
____
ns
t
OHZ
(1)
Outp ut Disab le to O utp ut in Hig h-Z
0
5
0
5
0
7
ns
t
OH
Outp ut Ho ld fro m A d d re ss Chang e
4
____
4
____
4
____
ns
t
PU
(1)
Chip S e le ct to P o we r-Up Tim e
0
____
0
____
0
____
ns
t
PD
(1)
Chip De s e le c t to P o we r-Do wn Tim e
____
12
____
15
____
20
ns
WRITE CYCLE
t
WC
Write Cy c le Tim e
12
____
15
____
20
____
ns
t
AW
A d d re ss V alid to End o f W rite
8
____
12
____
15
____
ns
t
CW
Chip S e le c t to E nd o f W rite
8
____
12
____
15
____
ns
t
AS
A d d re ss S e t-up Tim e
0
____
0
____
0
____
ns
t
WP
Write Pulse W id th
8
____
12
____
15
____
ns
t
WR
Write Re co v e ry Tim e
0
____
0
____
0
____
ns
t
DW
Data Valid to E nd -o f-Write
6
____
8
____
9
____
ns
t
DH
Data Ho ld Tim e
0
____
0
____
0
____
ns
t
OW
(1)
Outp ut active fro m End -o f-Write
3
____
3
____
4
____
ns
t
WHZ
(1)
W rite E nab le to Outp ut in Hig h-Z
0
5
0
5
0
8
ns
3514 tbl 09
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges
5
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
ADDRESS
3514 drw 05
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
.
DATA
OUT
ADDRESS
3514 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
.
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