NOVEMBER 2002
DSC-3624/06
1
2002 Integrated Device Technology, Inc.
Features
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x
x
x
x
256K x 16 advanced high-speed CMOS Static RAM
x
x
x
x
x
JEDEC Center Power / GND pinout for reduced noise.
x
x
x
x
x
Equal access and cycle times
Commercial and Industrial: 10/12/15ns
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x
One Chip Select plus one Output Enable pin
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x
x
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x
Bidirectional data inputs and outputs directly
LVTTL-compatible
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x
x
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x
Low power consumption via chip deselect
x
x
x
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x
Upper and Lower Byte Enable Pins
x
x
x
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x
Single 3.3V power supply
x
x
x
x
x
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
as 256K x 16. It is fabricated using IDT's high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V416 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Select
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A0 - A17
Row / Column
Decoders
CS
WE
BHE
BLE
4,194,304-bit
Memory
Array
Sense
Amps
and
Write
Drivers
16
High
Byte
Output
Buffer
High
Byte
Write
Buffer
Low
Byte
Write
Buffer
Low
Byte
Output
Buffer
8
8
8
8
8
8
8
8
I/O 15
I/O 8
I/O 7
I/O 0
3624 drw 01
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
IDT71V416S
IDT71V416L
6.42
2
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
*Pin 28 can either be a NC or connected to Vss
Top View
Pin Configurations - SOJ/TSOP
Pin Descriptions
SOJ Capacitance
(T
A
= +25C, f = 1.0MHz)
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O 7
A9
A8
A7
A6
A5
WE
I/O 6
I/O 5
I/O 4
V
SS
V
DD
I/O 3
I/O 2
I/O 1
I/O 0
CS
A4
A3
A2
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
A15
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
DD
I/O 11
I/O 10
I/O 9
I/O 8
A14
A13
A12
A11
A10
A17
NC*
SO44-1
SO44-2
3624 drw 02
A
0
- A
17
Address Inputs
Input
CS
Chip Select
Input
WE
Write Enable
Input
OE
Output Enable
Input
BHE
High Byte Enable
Input
BLE
Low Byte Enable
Input
I/O
0
- I/O
15
Data Input/Output
I/O
V
DD
3.3V Power
Pwr
V
SS
Ground
Gnd
3624 tbl 01
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
3624 tbl 02
1
2
3
4
5
6
A
BLE
OE
A
0
A
1
A
2
NC
B
I/O
0
BHE
A
3
A
4
CS
I/O
8
C
I/O
1
I/O
2
A
5
A
6
I/O
10
I/O
9
D
V
SS
I/O
3
A
17
A
7
I/O
11
V
DD
E
V
DD
I/O
4
NC
A
16
I/O
12
V
SS
F
I/O
6
I/O
5
A
14
A
15
I/O
13
I/O
14
G
I/O
7
NC
A
12
A
13
WE
I/O
15
H
NC
A
8
A
9
A
10
A
11
NC
3624 tbl 11
Pin Configurations - 48 BGA
48 BGA Capacitance
(T
A
= +25C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
6
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
3624 tbl 02b
6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
3
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply
Voltage
Recommended DC Operating
Conditions
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = 2V for pulse width less than 5ns, once per cycle.
Truth Table
(1)
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
Symbol
Rating
Value
Unit
V
DD
Supply Voltage Relative to V
SS
-0.5 to +4.6
V
V
IN,
V
OUT
Terminal Voltage Relative to
V
SS
-0.5 to V
DD
+0.5
V
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
1
W
I
OUT
DC Output Current
50
mA
3624 tbl 04
Grade
Temperature
V
SS
V
DD
Commercial
0
O
C to +70
O
C
0V
See Below
Industrial
40
O
C to +85
O
C
0V
See Below
3624 tbl 05
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
___ _
V
DD
+0.3
(1)
V
V
IL
Input Low Voltage
-0.3
(2)
___ _
0.8
V
3624 tbl 06
CS
OE
WE
BLE
BHE
I/O
0-
I/O
7
I/O
8-
I/O
15
Function
H
X
X
X
X
High-Z
High-Z
Deselected - Standby
L
L
H
L
H
DATA
OUT
High-Z
Low Byte Read
L
L
H
H
L
High-Z
DATA
OUT
High Byte Read
L
L
H
L
L
DATA
OUT
DATA
OUT
Word Read
L
X
L
L
L
DATA
IN
DATA
IN
Word Write
L
X
L
L
H
DATA
IN
High-Z
Low Byte Write
L
X
L
H
L
High-Z
DATA
IN
High Byte Write
L
H
H
X
X
High-Z
High-Z
Outputs Disabled
L
X
X
H
H
High-Z
High-Z
Outputs Disabled
3624 tbl 03
6.42
4
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, and t
WHZ
)
*Including jig and scope capacitance.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
Figures 1,2 and 3
3624 tbl 09
+1.5V
50
I/O
Z
0
= 50
3624 drw 03
30pF
3624 drw 04
320
350
5pF*
DATA
OUT
3.3V
IDT71V416S/71V416L
1
2
3
4
5
6
7
20 40
60 80 100 120 140 160 180 200
t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3624 drw 05
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics
(1, 2, 3)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
-0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol
Parameter
71V416S/L10
71V416S/L12
71V416S/L15
Unit
Com'l.
Ind.
(5)
Com'l.
Ind.
Com'l.
Ind.
I
CC
Dynamic Operating Current
CS < V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
200
200
180
180
170
170
mA
L
180
--
170
170
160
160
I
SB
Dynamic Standby Power Supply Current
CS > V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
70
70
60
60
50
50
mA
L
50
--
45
45
40
40
I
SB1
Full Standby Pow er Supply Current (static)
CS > V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
20
20
20
20
20
20
mA
L
10
--
10
10
10
10
3624 tbl 08
Symbol
Parameter
Test Conditions
IDT71V416
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
V
SS
to V
DD
___
5
A
|I
LO
|
Output Leakage Current
V
DD
= Max.,
CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
DD
= Min.
2.4
___
V
3624 tbl 07
6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
5
71V416S/L10
(2)
71V416S/L12
71V416S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
ns
t
CLZ
(1)
Chip Select Low to Output in Low-Z
4
____
4
____
4
____
ns
t
CHZ
(1)
Chip Select High to Output in High-Z
____
5
____
6
____
7
ns
t
OE
Output Enable Low to Output Valid
____
5
____
6
____
7
ns
t
OLZ
(1)
Output Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Enable High to Output in High-Z
____
5
____
6
____
7
ns
t
OH
Output Hold from Address Change
4
____
4
____
4
____
ns
t
BE
Byte Enable Low to Output Valid
____
5
____
6
____
7
ns
t
BLZ
(1)
Byte Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
t
BHZ
(1)
Byte Enable High to Output in High-Z
____
5
____
6
____
7
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
ns
t
AW
Address Valid to End of Write
8
____
8
____
10
____
ns
t
CW
Chip Select Low to End of Write
8
____
8
____
10
____
ns
t
BW
Byte Enable Low to End of Write
8
____
8
____
10
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
8
____
10
____
ns
t
DW
Data Valid to End of Write
5
____
6
____
7
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1)
Write Enable High to Output in Low-Z
3
____
3
____
3
____
ns
t
WHZ
(1)
Write Enable Low to Output in High-Z
____
6
____
7
____
7
ns
3624 tbl 10
Timing Waveform of Read Cycle No. 1
(1,2,3)
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0C to +70C temperature range only.
DATA
OUT
ADDRESS
36 2 4 drw 06
t
RC
t
AA
t
OH
D A T A
O UT
V AL ID
PREVIOUS DATA
OUT
VALID
t
OH
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3.
OE, BHE, and BLE are LOW.
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