NOVEMBER 2002
DSC-3623/04
1
2002 Integrated Device Technology, Inc.
Description
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-
nized as 1M x 4. It is fabricated using IDT's high-perfomance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
The IDT71V428 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs
and outputs of the IDT71V428 are LVTTL-compatible and operation is
from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.
Features
x
x
x
x
x
1M x 4 advanced high-speed CMOS Static RAM
x
x
x
x
x
JEDEC Center Power / GND pinout for reduced noise
x
x
x
x
x
Equal access and cycle times
-- Commercial and Industrial: 10/12/15ns
x
x
x
x
x
Single 3.3V power supply
x
x
x
x
x
One Chip Select plus one Output Enable pin
x
x
x
x
x
Bidirectional data inputs and outputs directly
LVTTL-compatible
x
x
x
x
x
Low power consumption via chip deselect
x
x
x
x
x
Available in 32-pin, 400 mil plastic SOJ package.
Functional Block Diagram
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
19
4
4
I/O
0
I/O
3
4
CONTROL
LOGIC
WE
OE
CS
3623 drw 01
3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
IDT71V428S
IDT71V428L
6.42
2
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
Pin Configuration
SOJ
Top View
Pin Description
Truth Table
(1,2)
Capacitance
(T
A
= +25C, f = 1.0MHz, SOJ package)
A
0
A
1
A
2
A
3
A
4
CS
I/O
0
V
DD
V
SS
I/O
1
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
19
A
18
A
17
A
16
A
15
OE
I/O
3
V
SS
V
DD
I/O
2
A
14
A
13
A
12
A
11
A
10
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SO32-3
3623 drw 02
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
V
HC
or
V
LC
.
A
0
A
19
Address Inputs
Input
CS
Chip Select
Input
WE
Write Enable
Input
OE
Output Enable
Input
I/O
0
- I/O
3
Data Input/Output
I/O
V
DD
3.3V Power
Power
V
SS
Ground
Gnd
3623 tbl 02
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
3623 tbl 03
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected - Standby (I
SB
)
V
HC
(3)
X
X
High-Z
Deselected - Standby (I
SB1
)
3623 tbl 01
6.42
3
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics
(1,2,3)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
2. V
IL
(min.) = 2V for pulse width less than 5ns, once per cycle.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
- 0.2V (High).
3. Power specifications are preliminary.
4. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol
Rating
Value
Unit
V
DD
Supply Voltage Relative to
V
SS
-0.5 to +4.6
V
V
IN
, V
OUT
Terminal Voltage Relative
to V
SS
-0.5 to V
DD
+0.5
V
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
1
W
I
OUT
DC Output Current
50
mA
3623 tbl 04
Grade
Temperature
V
SS
V
DD
Commercial
0C to +70C
0V
See Below
Industrial
40C to +85C
0V
See Below
3623 tbl 05
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
DD
+0.3
(1)
V
V
IL
Input Low Voltage
-0.3
(2)
____
0.8
V
3623 tbl 06
Symbol
Parameter
Test Condition
IDT71V428
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
V
DD
= Max., V
IN
= V
SS
to V
DD
___
5
A
|I
LO
|
Output Leakage Current
V
DD
= Max.,
CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
DD
= Min.
2.4
___
V
3623 tbl 07
71V428S/L10
71V428S/L12
71V428S/L15
Symbol
Parameter
Com'l.
Ind.
(5)
Com'l.
Ind.
Com'l.
Ind.
Unit
I
CC
Dynam ic Operating Current
CS
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
150
150
140
140
130
130
mA
L
140
--
130
130
120
120
mA
I
SB
Dynamic Standby Power Supply Current
CS
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S
60
60
50
50
40
40
mA
L
40
--
35
35
30
30
mA
I
SB1
Full Standby Power Supply Current (static)
CS
V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S
20
20
20
20
20
20
mA
L
10
--
10
10
10
10
mA
3623 tbl 08
6.42
4
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
+1.5V
50
I/O
Z
0
= 50
3623 drw 03
30pF
3623 drw 04
320
350
5pF*
DATA
OUT
3.3V
1
2
3
4
5
6
7
20 40
60 80 100 120 140 160 180 200
t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3623 drw 05
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3623 tbl 09
* Including jig and scope capacitance.
6.42
5
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= 3.3V 10%, Commercial and Industrial Temperature Ranges)
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0
C to +70
C temperature range only for low power 10ns (L10) speed grade.
71V428S/L10
(2)
71V428S/L12
71V428S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
5
____
6
____
7
ns
t
OE
Output Enable to Output Valid
____
5
____
6
____
7
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
5
____
6
____
7
ns
t
OH
Output Hold from Address Change
4
____
4
____
4
____
ns
t
PU
(1)
Chip Select to Power Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
10
____
12
____
15
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
ns
t
AW
Address Valid to End of Write
8
____
8
____
10
____
ns
t
CW
Chip Select to End of Write
8
____
8
____
10
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
8
____
10
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End of Write
6
____
6
____
7
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End of Write
3
____
3
____
3
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
6
____
7
____
7
ns
3623 tbl 10
6.42
6
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
ADDRESS
3623 drw 06
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
DD
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
DATA
OUT
ADDRESS
3623 drw 07
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
6.42
7
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No.1 (WE Controlled Timing)
(1,2,4)
NOTES:
1. A write occurs during the overlap of a LOW
CS and a LOW WE.
2.
OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and data to
be placed on the bus for the required t
DW
. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as
the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured 200mV from steady state.
Timing Waveform of Write Cycle No.2 (CS Controlled Timing)
(1,4)
ADDRESS
CS
WE
DATA
OUT
DATA
IN
3623 drw 08
(5)
(3)
(3)
(2)
(5)
(5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
t
AW
CS
ADDRESS
WE
3623 drw 09
DATA
IN
VALID
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
6.42
8
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
Ordering Information
X
Power
XX
Speed
XXX
Package
Y
32-pin 400-mil SOJ (S032-3)
10*
12
15
71V428
Device
Type
IDT
Speed in nanoseconds
3623 drw 10
S
L
X
Process/
Temperature
Range
Blank
I
Commercial (0
C to +70
C)
Industrial (40
C to +85
C)
Standard Power
Low Power
* Commercial only for low power (L10) speed grade and
Industrial only for standard power (S10) speed grade.
X
Die
Revision
Blank
YF
First Generation or current stepping being shipped
Second Generation die step
6.42
9
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit) Commercial and Industrial Temperature Ranges
Datasheet Document History
8/31/99
Updated to new format
Pg. 2
Added footnote for V
HC
in Truth Table
Pg. 4
Added footnote on jig and scope capacitance in Figure 2
Pg. 7
Revised footnote on Write Cycle No. 1 diagram
Pg. 9
Added Datasheet Document History
9/29/99
Pg. 19
Added Industrial temperature range offerings
11/26/02
Pg. 8
Updated ordering information for die revision
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
sramhelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
800-544-7726, x4033
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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