DECEMBER 1999

DSC-3821/03

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Pin Description Summary

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBT

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

Features

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the
need to control

Single R/

W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (

) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

Packaged in a JEDEC standard 100-pin TQFP package

clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.

The IDT71V546 contains data I/O, address and control signal regis-

ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.

A Clock Enable (

CEN) pin allows operation of the IDT71V546 to be

suspended as long as necessary. All synchronous inputs are ignored
when

CEN is high and the internal device registers will hold their previous

values.

There are three chip enable pins (

, CE

) that allow the user

to deselect the device when desired. If any one of these three is not active
when ADV/

LD is low, no new memory operation can be initiated and any

burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter. In the burst mode, the

IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the

LBO input

pin. The

LBO pin selects between linear and interleaved burst sequence.

The ADV/

LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/

LD = HIGH).

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.

IDT71V546

128K x 36, 3.3V Synchronous
SRAM with ZBT

Feature,

Burst Counter and Pipelined Outputs

- A

Address Inputs

Input

Synchronous

, CE

Three Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

Read/Write Signal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/

Advance Burst Address / Load New Address

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

Static

I/O

- I/O

, I/O

- I/O

Data Input/Output

I/O

Synchronous

3.3V Power

Supply

Static

Ground

Supply

Static

3821 tbl 01

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT

Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

- A

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/

LD Low, CEN Low and true

chip enables.

ADV/

Address/Load

N/A

ADV/

LD is a synchronous input that is used to load the internal registers with

new address and control when it is sampled low at the rising edge of clock with

the chip selected. When ADV/

LD is low with the chip deselected, any burst in

progress is terminated. When ADV/

LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/

LD is sampled high.

Read/Write

N/A

W signal is a synchronous input that identified whether the current load cycle

initiated is a Read or Write access to the memory array. The data bus activity for

the current cycle takes place two clock cycles later.

CEN

Clock Enable

LOW

Synchrono us Clock Enable Input. When

CEN is sampled high, all other

synchronous inputs, includ ing clock are ignored and outputs remain unchanged.

The effect of

CEN sampled high on the device outputs is as if the low to high

clock transition did not occur. For normal operation,

CEN must be sampled low

at rising edge of clock.

Individual Byte

Write Enables

LOW

Synchronous byte write enables. Enable 9-bit byte has its own active low byte

write enable. On load write cycles (When R/

W and ADV/LD are sampled low)

the appropriate byte write signal (

) must be valid. The byte write

signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/

W is sampled high. The appropriate byte(s) of data are written

into the device two cycles later.

can all be tied low if always doing

write to the entire 36-bit word.

Chip Enables

LOW

Synchro nous active low chip enable.

and

are used with CE

enable the IDT71V546. (

sampled high or CE

sampled low) and

ADV/

LD low at the rising edge of clock, initiates a deselect cycle. the ZBT

has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.

CE2

Chip Enable

HIGH

Synchronout active high chip enable. CE

is used with

and

to enable

the chip. CE

has inverted polarity but otherwise identical to

and

CLK

Clock

N/A

This is the clock input to the IDT71V546. Except for

OE, all timing references for

the device are made with respect to the rising edge of CLK.

I/O

- I/O

I/O

P1 -

I/O

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.

LBO

Linear Burst

Order

LOW

Burst order selection input. When

LBO is high the Interleaved burst sequence is

selected. When

LBO is low the Linear burst sequence is selected. LBO is a

static DC input.

Output Enable

LOW

Asynchronous output enable.

OE must be low to read data from the 71V546.

When

OE is high the I/O pins are in a high-impedance state. OE does not need

to be actively controlled for read and write cycles. In normal operation,

OE can

be tied low.

Power Supply

N/A

3.3V power supply input.

Ground

N/A

Ground pin.

3821 tbl 02

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT

Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Recommended Operating

Temperature and Supply Voltage

Recommended DC Operating

Conditions

Clk

Address A [0:16]

Control Logic

Address

Control

I
npu

i
s

t
e

3821 drw 01

Clock

Data I/O [0:31], I/O P[1:4]

Output Register

Mux

Sel

Gate

, CE

CEN

ADV/

LBO

128K x 36 BIT

MEMORY ARRAY

Grade

Temperature

Commercial

C to +70

3.3V±5%

Industrial

-40

C to +85

3.3V±5%

3821 tbl 03

NOTES:
1. V

(min.) = 1.0V for pulse width less than t

CYC/2

, once per cycle.

2. V

(max.) = +6.0V for pulse width less than t

CYC/2

, once per cycle.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

3.135

3.3

3.465

Ground

Input High Voltage - Inputs

2.0

____

4.6

Input High Voltage - I/O

2.0

____

+0.3

(2)

Input Low Voltage

-0.5

(1)

____

0.8

3821 tbl 04

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT

Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Capacitance

= +25°C, f = 1.0MHz, TQFP package)

Pin Configuration

Top View

TQFP

100 99 98 97 96 95 94 93 92 91 90

87 86 85 84 83 82 81

89 88

)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O

PK100-1

3821 drw 02

(1)

I/O

Symbol

Rating

Value

Unit

TERM

(2)

Terminal Voltage
with Respect to GND

-0.5 to +4.6

TERM

(3)

Terminal Voltage
with Respect to GND

-0.5 to V

+0.5

Operating Temperature

0 to +70

BIAS

Temperature Under Bias

-55 to +125

STG

Storage Temperature

-55 to +125

Power Dissipation

2.0

OUT

DC Output Current

3821 tbl 05

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

2. V

and Input terminals only.

3. I/O terminals.

NOTE:
1. This parameter is guaranteed by device characterization, but not production

tested.

Symbol

Parameter

(1)

Conditions

Max.

Unit

Input Capacitance

= 3dV

I/O

I/O Capacitance

OUT

= 3dV

3821 tbl 06

NOTES:
1. Pin 14 does not have to be connected directly to V

as long as the input voltage is > V

2. Pins 83 and 84 are reserved for future A

(8M) and A

(16M) respectively.

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT

Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table

(1)

Partial Truth Table for Writes

(1)

NOTES:
1. L = V

, H = V

, X = Don't Care.

2. When ADV/

LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/

W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (

, or

is sampled high or CE

is sampled low) and ADV/

LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When

CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires

= L,

= L, CE

= H on these chip enables. Chip is deselected if either one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.

CEN

Chip

(5)

Enable

ADV/

BWx

ADDRESS

USED

PREVIOUIS CYCLE

CURRENT CYCLE

I/O

(2 cycles later)

Select

Valid

External

LOAD WRITE

(7)

Select

External

LOAD READ

(7)

Valid

Internal

LOAD WRITE/

BURST WRITE

(Advance Burst Counter)

(2)

(7)

Internal

LOAD READ/

BURST READ

(Advance Burst Counter)

(2)

(7)

Deselect

DESELECT or STOP

(3)

HiZ

DESELECT / NOOP

NOOP

HiZ

SUSPEND

(4)

Previous Value

3821 tbl 07

NOTES:

1. L = V

, H = V

, X = Don't Care.

2. Multiple bytes may be selected during the same cycle.

Operation

READ

WRITE ALL BYTES

WRITE BYTE 1 (I/O [0:7], I/O

)

(2)

WRITE BYTE 2 (I/O [8:15], I/O

)

(2)

WRITE BYTE 3 (I/O [16:23], I/O

)

(2)

WRITE BYTE 4 (I/O [24:31], I/O

)

(2)

NO WRITE

3821 tbl 08

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