DECEMBER 2002

DSC-5298/03

Pin Description Summary

cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.

The IDT71V65703/5903 contain address, data-in and control signal

registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.

A Clock Enable (

CEN) pin allows operation of the IDT71V65703/5903

to be suspended as long as necessary. All synchronous inputs are ignored when
CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins (

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not
asserted when ADV/

LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.

The IDT71V65703/5903 have an on-chip burst counter. In the burst

mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the

LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/

LD signal is used to load a new

external address (ADV/

LD = LOW) or increment the internal burst counter

(ADV/

LD = HIGH).

The IDT71V65703/5903 SRAMs utilize IDT's latest high-performance

CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).

Features

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the
need to control

Single R/

W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT

, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

-A

Address Inputs

Input

Synchronous

, CE

Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

Read/Write Signal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/

Advance Burst Address/Load New Address

Input

Synchronous

LBO

Linear/Interleaved Burst Order

Input

Static

Sleep Mode

Input

Asynchronous

I/O

-I/O

, I/O

-I/O

Data Input/Output

I/O

Synchronous

, V

DDQ

Core Power, I/O Power

Supply

Static

Ground

Supply

Static

5298 tbl 01

IDT71V65703
IDT71V65903

256K x 36, 512K x 18
3.3V Synchronous ZBTTM SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

-A

Address Inputs

N/A

Synchro nous Address inputs. The address register is triggered by a co mbination of the rising edge of
CLK, ADV/

LD low, CEN low, and true chip enables.

ADV/

Advance / Load

N/A

ADV/

LD is a synchronous input that is used to load the internal registers with new address and control

when it is sample d low at the rising edge of clock with the chip selected. When ADV/LD is low with
the chip deselected, any burst in progress is terminated. When ADV/

LD is sampled high then the

inte rnal burst counter is advanced for any burst that was in progress. The external addresses are
ignored when ADV/

LD is sampled high.

Read / Write

N/A

W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or

Write access to the memory array. The data bus activity for the curre nt cycle takes place one clock

cycle later.

CEN

Clock Enable

LOW

Synchronous Clock Enable Input. When

CEN is sampled high, all other synchronous inputs, including

clock are ignored and outputs re main unchanged. The effect of

CEN sampled high on the device

outputs is as if the low to high clock transition did no t occur. For normal operation,

CEN must be

sampled low at rising edge of clock.

Individual Byte

Write Enables

LOW

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load

write cycles (When R/

W and ADV/LD are sampled low) the appropriate byte write signal (BW

)

must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/

W is sampled high. The appropriate byte(s) of data are written into the

device one cycle later.

can all be tied low if always doing write to the entire 36-bit word.

Chip Enables

LOW

Synchronous active low chip enable.

and

are used with CE

to enable the IDT71V65703/5903

(

sampled high or CE

sampled low) and ADV/

LD low at the rising edge of clock, initiates

a deselect cycle. The ZBT

has a one cycle deselect, i.e., the data b us will tri-state one clock cycle

after deselect is initiated.

Chip Enable

HIGH

Synchrono us active high chip enable. CE

is used with

and

to enable the chip. CE

has

inverted po larity but otherwise identical to

and

CLK

Clock

N/A

This is the clock input to the IDT71V65703/5903. Except for

OE, all timing references for the device are

made with respect to the rising edge of CLK.

I/O

-I/O

I/O

-I/O

Data Input/Output

I/O

N/A

Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).

LBO

Linear Burst

Order

LOW

Burst order selection input. When

LBO is high the Interleaved burst sequence is selected. When LBO

is low the Linear burst sequence is selected.

LBO is a static input, and it must not change during

device operation.

Output Enable

LOW

Asynchronous output enable.

OE must be low to read data from the 71V65703/5903. When OE is HIGH

the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
write cycles. In normal operation,

OE can be tied low.

Sleep Mode

HIGH

Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.

Power Supply

N/A

3.3V core power supply.

DDQ

Power Supply

N/A

3.3V I/O supply.

Ground

N/A

Ground.

5298 tbl 02

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram 512K x 18

Recommended DC Operating

Conditions

NOTE:
1. V

(min.) = 1.0V for pulse width less than t

CYC

/2, once per cycle.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.135

3.3

3.465

DDQ

I/O Supply Voltage

3.135

3.3

3.465

Ground

Input High Voltage - Inputs

2.0

____

+ 0.3

Input High Voltage - I/O

2.0

____

DDQ

+ 0.3

Input Low Voltage

-0.3

(1)

____

0.8

5298 tbl 04

Clk

Address A [0:18]

Control Logic

Address

Control

I
nput

egi

ster

5298 drw 01a

Clock

Data I/O [0:15], I/O P[1:2]

Mux

Sel

Gate

, CE

CEN

ADV/

LBO

512K x 18 BIT

MEMORY ARRAY

6.42

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBTTM SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Pin Configuration 256K x 36

NOTES:
1. Pins 14 and 66 do not have to be connected directly to V

as long as the input voltage is

2. Pin 16 does not have to be connected directly to V

as long as the input voltage is > V

3. Pins 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins TMS, TDI, TDO and TCK. The

current die revision allows these pins to be left unconnected, tied LOW (V

), or tied HIGH (V

Top View

100 TQFP

Grade

Temperature

(1)

DDQ

Commercial

0°C to +70°C

3.3V±5%

Industrial

-40°C to +85°C

3.3V±5%

5298 tbl 05

100 99 98 97 96 95 94 93 92 91 90

87 86 85 84 83 82 81

89 88

(3)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

)

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

5298 drw 02

(1)

I/O

(2)

I/O

(1)

I/O

NOTES:
1. T

is the "instant on" case temperature.

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