Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

DECEMBER 1999

DSC-2665/-

FEATURES:

· 25ns parallel port access time, 35ns cycle time
· 45MHz serial output shift rate
· Wide x16 organization offering easy expansion
· Low power consumption (50mA typical)
· Least/Most Significant Bit first read selected by asserting

the FL/DIR pin

· Four memory status flags: Empty, Full, Half-Full, and

Almost-Empty/Almost-Full

· Dual-Port zero fall-through architecture
· Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
· Industrial temperature range (40

C to +85

DESCRIPTION:

The IDT72105/72115/72125s are very high-speed, low-

power,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256, 512 and 1,024 word depths, respectively.

The ability to buffer wide word widths (x16) make these

FIFOs ideal for laser printers, FAX machines, local area

CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1,024 x 16

IDT72105
IDT72115
IDT72125

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

networks (LANs), video storage and disk/tape controller ap-
plications.

Expansion in width and depth can be achieved using

multiple chips. IDT's unique serial expansion logic makes this
possible using a minimum of pins.

The unique serial output port is driven by one data pin (SO)

and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.

Monitoring the FIFO is eased by the availability of four

status flags: Empty, Full, Half-Full and Almost-Empty/Almost-
Full. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-
Empty/Almost-Full Flag is available only in a single device
mode.

The IDT72105/72115/72125 are fabricated using IDT's

leading edge, submicron CMOS technology. Military grade
product is manufactured in compliance with the latest revision
of Mil-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

2665 drw 01

RESET

LOGIC

FLAG

LOGIC

SERIAL OUTPUT

LOGIC

WRITE

POINTER

RAM

ARRAY

256 x 16
512 x 16

1,024 x 16

READ

POINTER

015

EXPANSION

LOGIC

RSIX

RSOX

/DIR

SOCP

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

INDUSTRIAL TEMPERATURE RANGE

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16

PIN CONFIGURATION

PIN DESCRIPTIONS

PLASTIC THIN DIP (P28-2, order code: TP)

SOIC (SO28-3, order code: SO)

TOP VIEW

GND

RSOX/

/DIR

Vcc

SOCP

RSIX

2665 drw 02

Symbol

Name

I/O

Description

Inputs

Data inputs for 16-bit wide data.

Reset

When

is set low, internal READ and WRITE pointers are set to the first location of the RAM

array.

and

go HIGH.

and

AEF

go LOW. A reset is required before an initial WRITE

after power-up.

must be high during the

cycle. Also the First Load pin (

) is programmed

only during Reset.

Write

A write cycle is initiated on the falling edge of WRITE if the Full Flag (

) is not set. Data set-up

and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.

SOCP

Serial Output
Clock

A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (

) is not set. In

both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.

/DIR

First Load/
Direction

This is a dual purpose input used in the width and depth expansion configurations. The First
Load (

) function is programmed only during Reset (

) and a LOW on

indicates the first

device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.

RSIX

Read Serial In
Expansion

In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.

Serial Output

Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending

on the Direction pin programming. During Expansion the SO pins are tied together.

Full Flag

When

goes LOW, the device is full and further WRITE operations are inhibited. When

HIGH, the device is not full.

Empty Flag

When

goes LOW, the device is empty and further READ operations are inhibited. When

HIGH, the device is not empty.

Half-Full Flag

When

is LOW, the device is more than half-full. When

is HIGH, the device is empty to

half-full.

RSOX/

AEF

Read Serial
Out Expansion
Almost-Empty,
Almost-Full
Flag

This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an

AEF

output pin. When

AEF

is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When

AEF

is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX

connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.

Power Supply

Single power supply of 5V.

GND

Ground

Single ground of 0V.

2665 tbl 01

INDUSTRIAL TEMPERATURE RANGE

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16

Number of Words in FIFO

IDT72105

IDT72115

IDT72125

F
F
F
FFFFF

A
A

AEEEEFFFF

HFFFF

E
E
E
EFFFF

131

163

1127

32128

64256

128512

129224

257448

513896

225255

449511

8971023

256

512

1024

2665 tbl 02

STATUS FLAGS

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED DC OPERATING
CONDITIONS

Symbol

Rating

Commercial

Unit

TERM

Terminal Voltage with

0.5 to +7.0

Respect to GND

STG

Storage Temperature

55 to +125

OUT

DC Output Current

50 to +50

NOTE:

2665 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Supply Voltage

Input HIGH Voltage

2.0

(1)

Input LOW Voltage

0.8

Operating Temperature

-40

+85

NOTE:

2665 tbl 04

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Industrial: V

= 5.0V

10%, T

= -40

C to +85

NOTES:

2665 tbl 05

1. Measurements with 0.4V

CC.

2. SOCP = V

, 0.4

OUT

3. For SO, I

OUT

= 4mA.

4. For SO, I

OUT

= 16mA.

5. Tested with outputs open (I

OUT

= 0).

/DIR =

= V

- 0.2V; SOCP = 0.2V; all other inputs = V

- 0.2.

7. Measurements are made after reset.

IDT72105
IDT72115
IDT72125

Industrial

Symbol

Parameter

Min.

Typ.

Max.

Unit

(1)

Input Leakage Current (Any Input)

(2)

Output Leakage Current

Output Logic "1" Voltage I

OUT

= 2mA

(3)

2.4

Output Logic "0" Voltage I

OUT

= 8mA

(4)

0.4

CC1

(5)

Active Power Supply Current

100

CC2

(5,6,7)

Standby Current

(

/DIR = VIH; SOCP = VIL)

CC3

(5,6,7)

Power Down Current

INDUSTRIAL TEMPERATURE RANGE

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16

NOTE:

2665 tbl 06

1. Values guaranteed by design.

AC ELECTRICAL CHARACTERISTICS

(Industrial: V

= 5V

10%, T

= -40

C to +85

INDUSTRIAL

7 2 1 0 5 L 2 5

7 2 1 0 5 L 5 0

7 2 1 1 5 L 2 5

7 2 1 1 5 L 5 0

7 2 1 2 5 L 2 5

7 2 1 2 5 L 5 0

Symbol

P a r a m e t e r

Figure

M i n .

M a x .

M i n .

M a x .

Unit

Parallel Shift Frequency

28.5

MHz

SOCP

Serial Shift Frequency

MHz

PARALLEL INPUT TIMINGS

W C

Write Cycle Time

W P W

Write Pulse Width

W R

Write Recovery Time

Data Set-up Time

Data Hold Time

WEF

Write High to

HIGH

5, 6

WFF

Write Low to

LOW

4, 7

Write Low to Transitioning

AEF

WPF

Write Pulse Width After

HIGH

SERIAL OUTPUT TIMINGS

SOCP

Serial Clock Cycle Time

SOCW

Serial Clock Width HIGH/LOW

SOPD

SOCP Rising Edge to SO Valid Data

SOHZ

SOCP Rising Edge to SO at High-Z

(1)

SOLZ

SOCP Rising Edge to SO at Low-Z

(1)

SOCEF

SOCP Rising Edge to

LOW

5, 6

SOCFF

SOCP Rising Edge to

HIGH

4, 7

SOCF

SOCP Rising Edge to Transitioning

AEF

REFSO

SOCP Delay After

HIGH

RESET TIMINGS

RSC

Reset Cycle Time

Reset Pulse Width

RSS

Reset Set-up Time

RSR

Reset Recovery Time

EXPANSION MODE TIMINGS

FLS

Set-up Time to

Rising Edge

FLH

Hold Time to

Rising Edge

DIRS

DIR Set-up Time to SOCP Rising Edge

DIRH

DIR Hold Time from SOCP Rising Edge

SOXD1

SOCP Rising Edge to RSOX Rising
Edge

SOXD2

SOCP Rising Edge to RSOX Falling
Edge

SIXS

RSIX Set-up Time to SOCP Rising
Edge

SIXPW

RSIX Pulse Width

INDUSTRIAL TEMPERATURE RANGE

IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16

AC TEST CONDITIONS

2665 tbl 07

NOTES:
1.

and

AEF

may change status during Reset, but flags will be valid at t

RSC.

2. SOCP should be in the steady LOW or HIGH during t

RSS

. The first LOW-HIGH (or HIGH-LOW) transition can begin after t

RSR

Figure 1. Reset

FUNCTIONAL DESCRIPTION

Parallel Data Input

The device must be reset before beginning operation so

that all flags are set to their initial state. In width or depth
expansion the First Load pin (

) must be programmed to

indicate the first device.

The data is written into the FIFO in parallel through the D

input data lines. A write cycle is initiated on the falling edge

of the Write (

) signal provided the Full Flag (

) is not

asserted. If the

signal changes from HIGH-to-LOW and the

Full Flag (

) is already set, the write line is internally inhibited

internally from incrementing the write pointer and no write
operation occurs.

Data set-up and hold times must be met with respect to the

rising edge of Write. On the rising edge of

, the write pointer

is incremented. Write operations can occur simultaneously or
asynchronously with read operations.

Serial Data Output

The serial data is output on the SO pin. The data is clocked

out on the rising edge of SOCP providing the Empty Flag (

)

is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.

The serial word is shifted out Least Significant Bit or Most

Significant Bit first, depending on the

/DIR level during

operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.

CAPACITANCE

= +25

C, f = 1.0MHz)

Symbol

Parameter

(1)

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output
Capacitance

OUT

= 0V

NOTE:

2665 tbl 08

1. Characterized values, not currently tested.

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure A

2665 drw 03

1.1K

30pF

680

OUTPUT

or equivalent circuit

Figure A. Output Load

*Includes jig and scope capacitances.

RSC

FLAG
STABLE

2665 drw 04

RSC

RSS

RSR

RSC

SOCP

RSS

RSR

NOTE 2

FLS

FLH

/DIR

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