1
AUGUST 2001
IDT723626
IDT723636
IDT723646
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3271/3
CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2
1,024 x 36 x 2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
Memory storage capacity:
IDT723626 256 x 36 x 2
IDT723636 512 x 36 x 2
IDT723646 1,024 x 36 x 2
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using
EFA, EFB, FFA, and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (40
C to +85
C) is available
DESCRIPTION:
The IDT723626/723636/723646 is a monolithic, high-speed, low-
power, CMOS Triple Bus synchronous (clocked) FIFO memory which
supports clock frequencies up to 83 MHz and has read access times as fast as
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
R
A
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
WENC
Port-C
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
10
EFB
/ORB
AEB
18
18
FFC
/IRC
AFC
B
0
-B
17
FFA
/IRA
AFA
SPM
FS0/SD
FS1/
SEN
A
0
-A
35
EFA
/ORA
AEA
3271 drw01
36
36
Output Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
C
0
-C
17
CLKB
Port-B
Control
Logic
Common
Port
Control
Logic
(B and C)
BE
SIZEB
SIZEC
CLKC
MBC
36
36
36
36
Input Bus-
Matching
RENB
MBB
CSB
2
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
PIN CONFIGURATION
TQFP (PK128-1, order code: PF)
TOP VIEW
W/
R
A
CLKB
3271 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/
FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PRS2
Vcc
C17
C16
C15
C14
MBC
GND
C13
C12
C11
C10
C9
C8
Vcc
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
C0
GND
B17
B16
Vcc
B15
B14
B13
B12
GND
B11
B10
CSA
FFA
/IRA
EFA
/ORA
PRS1
Vcc
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
CLKC
GND
FS1/
SEN
MRS2
MBB
MBF1
Vcc
AEB
AFC
EFB
/ORB
FFC
/IRC
GND
CSB
WENC
RENB
A9
A8
A7
A
6
G
N
D
A
5
A4
A3
SPM
Vcc
A2
A1
A0
GND
B0
B1
B2
B3
B
4
B
5
GND
B
6
Vcc
B7
B8
B
9
104
103
INDEX
SIZEC
8 ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board
each chip buffer data between a bidirectional 36-bit bus (Port A) and two
unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO
data can be read out of Port B and written into Port C using either 18-bit or 9-
bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
DESCRIPTION (CONTINUED)
3
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (
MBF1 and MBF2) to signal when
new mail has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array and selects serial flag programming, parallel flag program-
ming, or one of three possible default flag offset settings, 8, 16 or 64. Each FIFO
has its own, independent Master Reset pin,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard
mode, the first word written to an empty FIFO is deposited into the memory
array. A read operation is required to access that word (along with all other
words residing in memory). In the First Word Fall Through mode (FWFT),
the first word written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFT pin
during Master Reset determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC).
The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB) and
a programmable Almost-Full flag (
AFA and AFC). AEA and AEB indicate when
a selected number of words remain in the FIFO memory.
AFA and AFC indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the Port
Clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA, and AEB are
two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for
AEA, AEB, AFA, AFC are loaded in parallel using Port
A or in serial via the SD input. The Serial Programming Mode pin (
SPM) makes
this selection. Three default offset settings are also provided. The
AEA and AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFC threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Master Reset.
Two or more FIFOs may be used in parallel to create wider data paths.
Such a width expansion requires no additional, external components. Further-
more, two IDT723626/723636/723646 FIFOs can be combined with unidirec-
tional FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip
will automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT723626/723636/723646s are characterized for operation from
0
C to 70
C. Industrial temperature range (40
C to +85
C) is available by
special order. They are fabricated using IDT's high speed, submicron CMOS
technology.
4
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port A Almost-Empty
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Flag
less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B Almost-Empty
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Flag
less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A Almost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Flag
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFC
Port C Almost-Full
O
Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations in
Flag
FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
B0-B17
Port B Data
O
18-bit output data port for side B.
BE/
FWFT
Big-Endian/
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this
First Word
case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B
Fall Through
data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select Little-Endian operation.
Select
In this case, the least significant byte or word on Port A is read from Port B first (A-to-B data flow) or is
written to Port C first (C-to-A data flow).
After Master Reset, this pin selects the timing mode. A HIGH on
FWFT selects IDT Standard mode, a LOW
selects First Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT must
be static throughout device operation.
C0-C17
Port C Data
I
18-bit input data port for side C.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB.
FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincident to CLKA.
EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKC
Port C Clock
I
CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous
or coincident to CLKA.
FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
CSA
Port A Chip Select
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17
outputs are in the high-impedance state when
CSB is HIGH.
EFA/ORA
Port A Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFA function is selected. EFA indicates whether
Output Ready Flag
or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the
presence of valid data on the A0-A35 outputs, available for reading.
EFA/ORA is synchronized to the
LOW-to-HIGH transition of CLKA.
EFB/ORB
Port B Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFB function is selected. EFB indicates whether
Output Ready Flag
or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the
presence of valid data on the B0-B17 outputs, available for reading.
EFB/ORB is synchronized to the
LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
FFA/IRA
Port A Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFA function is selected. FFA indicates whether
Input Ready Flag
or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory.
FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFC function is selected. FFC indicates whether
Input Ready Flag
or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC indicates whether or
not there is space available for writing to the FIFO2 memory.
FFC/IRC is synchronized to the
LOW-to-HIGH transition of CLKC.
5
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
Description
FS1/
SEN Flag Offset
I
FS1/
SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
Select 1/
FS1/
SEN and FS0/SD, together with SPM, select the flag offset programming method. Three Offset register
Serial Enable,
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
from Port A, and serial FS0/SD load.
Flag Offset
I
Select 0/
When serial load is selected for flag Offset register programming, FS1/
SEN is used as an enable synchronous to
Serial Data
the LOW-to-HIGH transition of CLKA. When FS1/
SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 32 for the
IDT723626, 36 for the IDT723636, and 40 for the IDT723646. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs
Select
are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2
output-register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
Select
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC
Port C Mailbox
I
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Select
Master Reset.
MBF1
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
Master Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on
MRS1 selects the programming method (serial or parallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and C for bus size
and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while
MRS1 is LOW.
MRS2
Master Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output
register to all zeroes. A LOW-to-HIGH transition on
MRS2 toggled simultaneously with MRS1, selects the programming
method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA
and four LOW-to-HIGH transitions of CLKC must occur while
MRS2 is LOW.
PRS1
Partial Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.
PRS2
Partial Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained.
RENB
Port B Read Enable
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
SIZEB
(1)
Port B
I
SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select
selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC
(1)
Port C
I
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select
selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEC must be static throughout device operation.
SPM
(1)
Serial Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming
Mode
or default offsets (8, 16, or 64).
WENC
Port C Write Enable
I
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/
RA
Port A Write/Read
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
Select
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
NOTE:
1. SIZEB, SIZEC and
SPM are not TTL compatible. These inputs should be tied to GND or VCC.
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