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Электронный компонент: 723641

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SEPTEMBER 2002
DSC-2023/5
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
CMOS SyncFIFOTM
512 x 36
1,024 x 36
2,048 x 36
IDT723631
IDT723641
IDT723651
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:




Storage capacity:
IDT723631 - 512 x 36
IDT723641 - 1,024 x 36
IDT723651 - 2,048 x 36




Supports clock frequencies up to 67 MHz




Fast access times of 11ns




Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)




Clocked FIFO buffering data from Port A to Port B




Synchronous read retransmit capability




Mailbox register in each direction




Programmable Almost-Full and Almost-Empty flags




Microprocessor interface control logic




Input Ready (
IR) and Almost-Full (AF) flags synchronized by
CLKA




Output Ready (
OR) and Almost-Empty (AE) flags synchronized
by CLKB




Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)




Industrial temperature range (40C to +85C) is available
DESCRIPTION:
The IDT723631/723641/723651 is a monolithic high-speed, low-power,
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz
and has read access times as fast as 12ns. The 512/1,024/2,048 x 36
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory
has retransmit capability, which allows previously read data to be ac-
cessed again. The FIFO has flags to indicate empty and full conditions and
two programmable flags (Almost-Full and Almost-Empty) to indicate when a
selected number of words is stored in memory. Communication between
each port may take place with two 36-bit mailbox registers. Each mailbox
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
OR
AE
B
0
- B
35
3023 drw01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
MBF2
IR
AF
FS
0
/SD
FS
1
/
SEN
Flag Offset
Registers
A
0
- A
35
10
Sync
Retransmit
Logic
RTM
RFM
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
36
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFOTM
512 x 36, 1,024 x 36 and 2,048 x 36
DESCRIPTION (CONTINUED)
NOTES:
1. NC No Connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
PIN CONFIGURATION
NC
NC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
NC
NC
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3023 drw02
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
NC B
11
B
10
B
9
B
7
B
8
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
NC
NC
NC V
CC
CLKB
ENB
W
/RB
CSB GND
RFM
RTM
V
CC
MBF1
MBB
FS1/
SEN
GND
FS0/SD
RST MBA MBF2
AE AF V
CC
IR
CSA
W/
R
A
ENA
CLKA
GND
GND
NC
V
CC
OR
*
register has a flag to signal when new mail has been stored. Two or more
devices may be used in parallel to create wider data paths. Expansion is
also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a continuous (free-running) port clock by en-
able signals. The continuous clocks for each port are independent of one
another and can be asynchronous or coincident. The enables for each
port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The Input Ready (IR) flag and Almost-Full (
AF) flag of the FIFO are
two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-
most-Empty (
AE) flag of the FIFO are two-stage synchronized to CLKB.
Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be
programmed from port A or through a serial input.
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFOTM
512 x 36, 1,024 x 36 and 2,048 x 36
3
PIN CONFIGURATION (CONTINUED)
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
NOTE:
1. NC No Connection
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
3023 drw03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
CLKA
ENA
W/
R
A
CSA IR OR V
CC
AF AE VCC MBF2 MBA RST GND FS0/SD FS1/
SEN
RTM
RFM
V
CC
NC MBB
GND
MBF1 GND CSB W
/RB
ENB
CLKB
V
CC
B
11
B
9
B
10
B
7
B
8
B
6
B
0
B
1
B
2
B
3
B
4
B
5
GND
V
CC
GND
A
0
A
1
A
3
A
4
A
2
A
5
V
CC
GND
GND
GND
A
11
A
10
A
9
A
8
A
7
A
6
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFOTM
512 x 36, 1,024 x 36 and 2,048 x 36
PIN DESCRIPTION
Symbol
Name
I/O
Description
A0-A35
Port-A Data
I/O
36-bit bidirectional data port for side A.
AE
Almost-Empty
O
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in
Flag
the Almost-Empty register (X).
AF
Almost-Full
O
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO is less than or equal to the
Flag
value in the Almost-Full Offset register (Y).
B0-B35
Port-B Data
I/O
36-bit bidirectional data port for side B.
CLKA
Port-A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or coincident to CLKB.
IR and
AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB
Port-B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA.
OR and
AE are synchronous to the LOW-to-HIGH transition of CLKB.
CSA
Port-A Chip
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the
Select
high-impedance state when
CSA is HIGH.
CSB
Port-B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the
Select
high-impedance state when
CSB is HIGH.
ENA
Port-A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB
Port-B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FS1/
Flag-Offset
I
FS1/
SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset, FS1/SEN and
SEN,
Select 1/
FS0/SD selects the flag offset programming method. Three Offset register programming methods are available: automatically
Serial Enable
load one of two preset values, parallel load from port A, and serial load.
FS0/SD
Flag Offset 0/
When serial load is selected for flag Offset register programming, FS1/
SEN is used as an enable synchronous to the LOW-to-
Serial Data
HIGH transition of CLKA. When FS1/
SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y
registers. The number of bit writes required to program the Offset registers is 18/20/22. The first bit write stores the Y-register
MSB and the last bit write stores the X-register LSB.
IR
Input Ready
O
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are
Flag
disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit
data and prevents further writes. IR is set LOW during reset and is set HIGH after reset.
MBA
Port-A Mailbox
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
Select
MBB
Port-B Mailbox
I
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH
Select
level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a
Flag
LOW-to-HIGH transition of CLKB when a port-B readis selected and MBB is HIGH.
MBF1 is set HIGH by a reset.
MBF2
Mail2 Register
O
MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a
Flag
LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH.
MBF2 is set HIGH by a reset.
OR
Output Ready
O
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled.
Flag
Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes
HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
RFM
Read From
I
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer
Mark
to the beginning retransmit location and output the first selected retransmit data.
RST
Reset
I
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
RST
is LOW. The LOW-to-HIGH transition of
RST latches the status of FS0 and FS1 for AF and AE offset selection.
RTM
Retransmit
I
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB
Mode
selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial
retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode.
W/
RA
Port-A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The
Read Select
A0-A35 outputs are in the high-impedance state when W/
RA is HIGH.
W/RB
Port-B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The
Read Select
B0-B35 outputs are in the high-impedance state when
W/RB is LOW.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFOTM
512 x 36, 1,024 x 36 and 2,048 x 36
5
IDT723631
IDT723641
IDT723651
Commercial & Industrial
(1)
t
A
= 15, 20 ns
Parameter
Test Conditions
Min.
Typ.
(2)
Max.
Unit
V
OH
V
CC
= 4.5V,
I
OH
= 4 mA
2.4
--
--
V
V
OL
V
CC
= 4.5V,
I
OL
= 8 mA
--
--
0.5
V
I
LI
V
CC
= 5.5V,
V
I
= VCC or 0
--
--
5
A
I
LO
V
CC
= 5.5V,
V
O
= VCC or 0
--
--
5
A
I
CC
V
CC
= 5.5V,
V
I
= VCC 0.2V or 0
--
--
400
A
I
CC
(3,4)
V
CC
= 5.5V,
One Input at 3.4V,
CSA = VIH
A0-A35
--
0
--
mA
Other Inputs at V
CC
or GND
CSB = VIH
B0-B35
--
0
--
CSA = VIL
A0-A35
--
--
1
CSB = VIL
B0-35
--
--
1
All Other Inputs
--
--
1
C
IN
V
I
= 0,
f = 1 MHz
--
4
--
pF
C
OUT
V
O
= 0,
f = 1 MHZ
--
8
--
pF
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
RANGE (UNLESS OTHERWISE NOTED)
(2)
Symbol
Rating
Commercial
Unit
V
CC
Supply Voltage Range
0.5 to 7
V
V
I
(2)
Input Voltage Range
0.5 to VCC+0.5
V
V
O
(2)
Output Voltage Range
0.5 to VCC+0.5
V
I
IK
Input Clamp Current, (V
I
< 0 or V
I
> V
CC
)
20
mA
I
OK
Output Clamp Current, (V
O
= < 0 or V
O
> V
CC
)
50
mA
I
OUT
Continuous Output Current, (V
O
= 0 to V
CC
)
50
mA
I
CC
Continuous Current Through V
CC
or GND
400
mA
T
STG
Storage Temperature Range
65 to 150
C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. All typical values are at V
CC
= 5V, T
A
= 25
C.
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or V
CC
.
4. For additional I
CC
information, see the following page.
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage
4.5
5.5
V
V
IH
HIGH Level Input Voltage
2
--
V
V
IL
LOW-Level Input Voltage
--
0.8
V
I
OH
HIGH-Level Output Current
--
4
mA
I
OL
LOW-Level Output Current
--
8
mA
T
A
Operating Free-air Temperature
0
70
C
RECOMMENDED OPERATING CONDITIONS