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APRIL 2003
DSC-6163/1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
PRELIMINARY
IDT72V15160
IDT72V14320
IDT72V16160
IDT72V15320
IDT72V17160
IDT72V16320
IDT72V18160
IDT72V17320
IDT72V19160
IDT72V18320
IDT72V19320
FEATURES:




Choose among the following memory organizations: Commercial
V-III
Vx-III
IDT72V15160 - 4,096 x 16
IDT72V14320 - 1,024 x 32
IDT72V16160 - 8,192 x 16
IDT72V15320 - 2,048 x 32
IDT72V17160 - 16,384 x 16
IDT72V16320 - 4,096 x 32
IDT72V18160 - 32,768 x 16
IDT72V17320 - 8,192 x 32
IDT72V19160 - 65,536 x 16
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32




Up to 100 MHz Operation of the Clocks




5V input tolerant




Auto power down minimizes standby power consumption




Master Reset clears entire FIFO




Partial Reset clears data, but retains programmable settings




Empty, Full and Half-Full flags signal FIFO status




Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets




Program programmable flags through serial input




Output enable puts data outputs into high impedance state




JTAG port, provided for Boundary Scan function (PBGA Only)




Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)




Industrial temperature range (40


C to +85C)




High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*
Available on the Vx-III PBGA package only.
RESET LOGIC
FLAG LOGIC
WRITE
CONTROL
READ
CONTROL
FIFO ARRAY
WCLK
WEN
D0 - Dn
Data In
x16, x32
MRS
HF
PAF
Q0 - Qn
Data Out
x16, x32
RCLK
REN
FF
OE
PRS
PAE
EF
SI
SEN
LD
FSEL0
PFM
FSEL1
6163 drw01
JTAG CONTROL
(BOUNDARY
SCAN)
TCK
TMS
TDO
TDI
TRST
*
*
*
*
*
*
2
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
TQFP (PN80-1, order code: PF)
TOP VIEW
DESCRIPTION:
The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with independent clocked
read and write controls and high density offerings up to 1 Mbit.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
). The
frequencies of both the RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to f
S
(
MAX)
with complete independence.
There are no restrictions on the frequency of the one clock input with respect
to the other.
These FIFOs have five flag pins,
EF (Empty Flag), FF (Full Flag), HF (Half-
full Flag),
PAE (Programmable Almost-Empty flag) and PAF (Programmable
Almost-Full flag).
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded with the serial interface to any user desired value or by default values.
Eight default offset settings are provided, so that
PAE can be set to switch at a
predefined number of locations from the empty boundary and the
PAF threshold
can also be set at similar predefined values from the full boundary. The default
offset values are set during Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming,
SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI).
During Master Reset (
MRS) the read and write pointers are set to the first
location of the FIFO.
NOTE:
1. DNC = Do Not Connect.
DNC
(1)
OE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GND
GND
D0
D1
D2
GND
D3
GND
D4
D5
D6
D7
D8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
59
V
CC
Q0
GND
GND
DNC
(1)
Q2
Q3
Q4
Q5
GND
Q7
Q8
Q9
INDEX
WEN
SEN
DNC
(1)
Q6
V
CC
6163 drw02
20
1
V
CC
V
CC
V
CC
GND
V
CC
V
CC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
79
WCLK
PRS
MRS
LD
SI
FF
PAF
GND
FSEL0
HF
FSEL1
GND
GND
V
CC
PAE
PFM
EF
GND
RCLK
REN
D9
GND
GND
D10
D11
D12
D13
D14
D15
GND
Q15
Q14
GND
Q13
Q12
V
CC
Q11
Q10
GND
DNC
(1)
Q1
3
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TQFP: (PK128-1, order code: PF)
TOP VIEW
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the programmable flag settings existing before
Partial Reset remain unchanged.
PRS is useful for resetting a device in mid-
operation, when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE (Programmable Almost-
Empty flag) and
PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE and
PAF flags.
If asynchronous
PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the
PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT V-III and Vx-III family of FIFOs are fabricated using IDT's high
speed submicron CMOS technology.
PIN CONFIGURATIONS (32-BIT Vx-III FAMILY)
V
CC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
D4
V
CC
D5
GND
D6
D7
D8
GND
D9
D10
GND
GND
D11
D12
D13
D14
D15
GND
D16
D17
GND
V
CC
D19
D20
GND
D21
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
Q0
GND
GND
Q4
Q5
Q6
Q7
Q8
DNC
(1)
Q9
Q10
GND
GND
DNC
(1)
Q11
Q12
Q13
Q14
Q15
GND
Q16
Q17
DNC
(1)
Q18
Q19
Q20
GND
Q21
Q22
INDEX
WEN
SEN
DNC
(1)
D18
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DNC
(1)
V
CC
REN
RCLK
PAE
PFM
EF
GND
GND
V
CC
GND
GND
GND
FS1
GND
HF
FS0
GND
GND
PAF
V
CC
FF
SI
LD
MRS
PRS
WCLK
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
D22
D23
D24
D25
GND
GND
D26
D27
D29
D30
D31
GND
Q31
Q30
Q29
Q28
Q27
Q26
GND
DNC
(1)
Q25
Q23
104
103
Q24
V
CC
V
CC
D28
D0
D1
D2
D3
Q1
Q2
Q3
6163 drw03
NOTE:
1. DNC - Do Not Connect.
4
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
PIN CONFIGURATIONS-CONTINUED (32-BIT VX-III FAMILY)
NOTE:
1. DNC - Do Not Connect.
WEN
WCLK
PAF
FF
HF
GND
EF
RCLK
REN
OE
Q0
SEN
GND
PRS
LD
MRS
FS0
FS1
V
CC
GND
PFM
V
CC
Q1
D0
D1
D2
SI
GND
V
CC
V
CC
GND
PAE
GND
Q3
Q2
D3
D4
D5
V
CC
V
CC
GND
GND
V
CC
V
CC
Q6
Q5
Q4
D6
D9
D8
V
CC
Q9
Q8
Q7
D7
D10
D11
Q12
Q11
Q10
D14
D13
D12
Q13
Q14
Q15
D17
D16
D15
V
CC
Q16
Q17
Q18
D20
D19
D18
V
CC
Q19
Q20 Q21
D23
D22
D21
D28
D31
V
CC
V
CC
TDO
Q29
Q22
Q23
D25
D27
D30
TMS
TCK
Q31
Q28
Q26
D24
D26
D29
TRST
TDI
Q30
Q27
Q25
Q24
DNC
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
6163 drw03b
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
GND
GND
GND
GND
V
CC
GND
GND
V
CC
V
CC
GND
GND
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
DNC
DNC
DNC
5
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
PIN DESCRIPTION
Symbol
Name
I/O
Description
D
0
Dn
Data Inputs
I
Data inputs for a 16 or 32-bit bus
EF
Empty Flag
O
EF indicates the FIFO memory is empty. See Table 2.
FF
Full Flag
O
FF indicates the FIFO memory is full. See Table 2.
FSEL0
(1)
Flag Select Bit 0
I
During Master Reset, this input along with FSEL1 and the
LD pin, will select the default offset values for the
programmable flags
PAE and PAF. There are up to eight possible settings available.
FSEL1
(1)
Flag Select Bit 1
I
During Master Reset, this input along with FSEL0 and the
LD pin will select the default offset values for the
programmable flags
PAE and PAF. There are up to eight possible settings available.
HF
Half-Full Flag
O
HF indicates the FIFO memory is more than half-full. HF is asserted when the number of words written into the FIFO
reaches N
2+1, where N is the total depth of the FIFO. See Table 2.
LD
Load
I
During Master Reset, the state of the
LD input along with FSEL0 and FSEL1, determines one of eight default offset
values for the
PAE and PAF flags and serial programming mode. After Master Reset, LD must be high and should
only toggle LOW together with
SEN to start serial loading of the flag offsets.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for one of eight programmable flag default settings, serial programming of the offset settings and
synchronous versus asynchronous programmable flag timing modes.
OE
Output Enable
I
OE controls the output line drivers
.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register.
PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
O
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register.
PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM
(1)
Programmable
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode
will select Synchronous Programmable flag timing mode.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the serial programming method or programmable flag settings are all retained.
Q
0
Qn
Data Outputs
O
Data outputs for an 16 or 32-bit bus. Outputs are not 5V tolerant regardless of the state of
OE.
RCLK
Read Clock
I
When enabled by
REN, the rising edge of RCLK reads data from the FIFO memory.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory.
SEN
Serial Enable
I
SEN enables serial loading of programmable flag offsets. SEN must be high during Master Reset and should only
toggle LOW together with
LD to start serial loading of the flag offsets.
SI
Serial In
I
At Maser Reset this pin is LOW. After Master Reset, this pin functions as a serial input for loading offset registers.
WCLK
Write Clock
I
Enabled by
WEN, the rising edge of WCLK writes data into the FIFO.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory.
V
CC
+3.3V Supply
I
These are V
CC
supply inputs and must be connected to the 3.3V supply rail.
GND
Ground
I
Ground Pins.
NOTE:
1. Inputs should not change state after Master Reset.
**Please continue to next page for more Pin descriptions for PBGA package.
6
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
PIN DESCRIPTION (32-BIT VX-III PBGA PACKAGE ONLY)
Symbol
Name
I/O
Description
TCK
(1)
JTAG Clock
I
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI
(1)
JTAG Test Data
I
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input
serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(1)
JTAG Test Data
O
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output
serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS
(1)
JTAG Mode Select
I
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
(1)
JTAG Reset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use
TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces
TRST HIGH if
left unconnected.
NOTE:
1. These pins are for the JTAG port. Please refer to pages 15-19 and Figures 2-4.
7
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Industrial
Unit
V
TERM
(2)
Terminal Voltage
0.5 to +4.5
V
with respect to GND
T
STG
Storage
55 to +125
C
Temperature
I
OUT
DC Output Current
50 to +50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
NOTES:
1. With output deselected, (
OE
V
IH
).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 3.3V 0.15V, T
A
= -40
C to +85C; JEDEC JESD8-A compliant)
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2)
Input
V
IN
= 0V
10
pF
Capacitance
C
OUT
(1,2)
Output
V
OUT
= 0V
10
pF
Capacitance
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
(1)
Supply Voltage Industrial
3.15
3.3
3.45
V
GND
Supply Voltage Industrial
0
0
0
V
V
IH
(2)
Input High Voltage Industrial
2.0
--
5.5
V
V
IL
(3)
Input Low Voltage Industrial
--
--
0.8
V
T
A
Operating Temperature Industrial
-40
--
85
C
NOTES:
1. V
CC
= 3.3V 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
IDT72V15160,
IDT72V14320
IDT72V16160,
IDT72V15320
IDT72V17160,
IDT72V16320
IDT72V18160,
IDT72V17320
IDT72V19160,
IDT72V18320
IDT72V19320
Industrial
t
CLK
= 10ns
Symbol
Parameter
Min.
Max.
Unit
I
LI
(1)
Input Leakage Current
1
1
A
I
LO
(2)
Output Leakage Current
10
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2 mA
2.4
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8 mA
--
0.4
V
I
CC1
(3,4,5)
Active Power Supply Current
--
40
mA
I
CC2
(3,6)
Standby Current
--
15
mA
NOTES
:
1. Measurements with 0.4
V
IN
V
CC
.
2.
OE
V
IH,
0.4
V
OUT
V
CC.
3. Tested with outputs open (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 4.2 + 1.4*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 3.3V, t
A
= 25
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2,
C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
RECOMMENDED DC OPERATING
CONDITIONS
8
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 3.3V 0.15V, T
A
= -40
C to +85C; JEDEC JESD8-A compliant)
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
Industrial
IDT72V15160L10
IDT72V14320L10
IDT72V16160L10
IDT72V15320L10
IDT72V17160L10
IDT72V16320L10
IDT72V18160L10
IDT72V17320L10
IDT72V19160L10
IDT72V18320L10
IDT72V19320L10
Symbol
Parameter
Min.
Max
Unit
f
S
Clock Cycle Frequency
--
100
Mhz
t
A
Data Access Time
2
6.5
ns
t
CLK
Clock Cycle Time
10
--
ns
t
CLKH
Clock High Time
4.5
--
ns
t
CLKL
Clock Low Time
4.5
--
ns
t
DS
Data Setup Time
3.5
--
ns
t
DH
Data Hold Time
0.5
--
ns
t
ENS
Enable Setup Time
3.5
--
ns
t
ENH
Enable Hold Time
0.5
--
ns
t
LDS
Load Setup Time
3.5
--
ns
t
LDH
Load Hold Time
0.5
--
ns
t
RS
Reset Pulse Width
(1)
10
--
ns
t
RSS
Reset Setup Time
15
--
ns
t
RSR
Reset Recovery Time
10
--
ns
t
RSF
Reset to Flag and Output Time
--
15
ns
t
OLZ
Output Enable to Output in Low Z
(2)
0
--
ns
t
OE
Output Enable to Output Valid
2
6
ns
t
OHZ
Output Enable to Output in High-Z
(2)
2
6
ns
t
WFF
Write Clock to
FF
--
6.5
ns
t
REF
Read Clock to
EF
--
6.5
ns
t
PAFA
Clock to Asynchronous Programmable Almost-Full Flag
--
16
ns
t
PAFS
Write Clock to Synchronous Programmable Almost-Full Flag
--
6.5
ns
t
PAEA
Clock to Asynchronous Programmable Almost-Empty Flag
--
16
ns
t
PAES
Read Clock to Synchronous Programmable Almost-Empty Flag
--
6.5
ns
t
HF
Clock to
HF
--
16
ns
t
SKEW1
Skew time between RCLK and WCLK for
EF and FF
7
--
ns
t
SKEW2
Skew time between RCLK and WCLK for
PAE and PAF
10
--
ns
9
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
(1)
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load for t
CLK
= 10ns
See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
AC TEST LOADS
V
IH
OE
V
IL
t
OE &
t
OLZ
V
CC
2
V
CC
2
100mV
100mV
t
OHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
V
CC
2
6163 drw04a
Output
Enable
Output
Disable
OUTPUT ENABLE & DISABLE TIMING
NOTE:
1.
REN is HIGH.
6163 drw04
330
30pF*
510
3.3V
D.U.T.
10
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
IDT72V14320, 72V15360
LD
FSEL1
FSEL0
Offsets n,m
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
L
L
31
H
H
L
15
H
L
H
7
H
H
H
3
IDT72V16320, 72V17320, 72V18320, 72V19320
IDT72V15160, 72V16160, 72V17160, 72V18160
LD
FSEL1
FSEL0
Offsets n,m
H
L
L
1,023
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
H
L
31
H
L
H
15
H
H
H
7
IDT72V19160
LD
FSEL1
FSEL0
Offsets n,m
H
L
L
1,023
L
H
L
8,191
L
L
H
16,383
L
L
L
127
L
H
H
4,095
H
H
L
511
H
L
H
2,047
H
H
H
255
All Devices
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial
(3)
TABLE 1 -- DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
FUNCTIONAL DESCRIPTION
To write data into to the FIFO, Write Enable (
WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (
EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The
Programmable Almost-Empty flag (
PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where "n" is the empty offset value. The default setting
for these values are stated in the footnote of Table 1. This parameter is also user
programmable.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (
HF) would toggle to LOW once
D/2+1 (D= total number of words) was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (
PAF) to go
LOW. Again, if no reads are performed, the
PAF will go LOW after (D-m). The
offset "m" is the full offset value. The default setting for these values are stated
in the footnote of Table 1. This parameter is also user programmable.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
FF will go LOW after D writes
to the FIFO.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and HF to go HIGH. If further read
operations occur, without write operations,
PAE will go LOW when there are
n words in the FIFO, where n is the empty offset value. Continuing read
operations will cause the FIFO to become empty. When the last word has been
read from the FIFO, the
EF will go LOW inhibiting further read operations. REN
is ignored when the FIFO is empty.
The
EF and FF outputs are double register-buffered outputs.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT V-III
and Vx-III FIFOs have internal registers for these offsets.
There are two ways to program the flag offset values. Selecting one of the
eight pre-set values during master reset or serial programming.
DEFAULT FLAG OFFSETS
There are eight default offset values selectable during Master Reset. These
offset values are shown in Table 1.
Programming offsets with default values (
LD, SEN pins): With the
LD pin together with the FSEL0 and FSEL1 the user has the option to choose
one of eight preset values for both offset registers. During master reset the
LD
pin can be either HIGH or LOW depending on the selected value. After Master
Reset,
LD must be high and should not change state. SEN should be high during
and after Master Reset and should not change state.
A total of
20 bits for the IDT72V14320
22 bits for the IDT72V15320
24 bits for the IDT72V15160, IDT72V16320
26 bits for the IDT72V16160, IDT72V17320
28 bits for the IDT72V17160, IDT72V18320
30 bits for the IDT72V18160, IDT72V19320
32 bits for the IDT72V19160
has to be loaded serial for the two (
PAF, PAE) registers.
SERIAL PROGRAMMING MODE
Offset values can also be programmed into the FIFO by serial loading
method. The offset registers may be programmed (and reprogrammed) any
time after Master Reset. Valid programming ranges are from 0 to D-1.
Serial programming of offset values (
LD,SEN pins): In order to select
serial programming the
LD pin has to be HIGH during master. Both, LD and
SEN pin have to toggle to LOW in order to initial the serial programming. LD
should be high during normal FIFO operation.
If Serial Programming mode has been selected then programming of
PAE
and
PAF values can be achieved by using a combination of the LD, SEN, WCLK
and SI input pins. Programming
PAE and PAF proceeds as follows: when LD
and
SEN are set LOW, data on the SI input are written, one bit for each WCLK
rising edge, starting with the Empty Offset LSB and ending with the Full Offset
MSB.
11
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
6163 drw05
TABLE 2
STATUS FLAGS FOR IDT STANDARD MODE
FF PAF HF PAE EF
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
L
H
H
0
1 to n
(1)
(n+1) to 512
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,024
IDT72V14320
0
0
(n+1) to 1,024
(n+1) to 2,048
1,025 to (2,048-(m+1))
2,049 to (4,096-(m+1))
(2,048-m) to 2,047
(4,096m) to 4,095
2,048
4,096
FF PAF HF PAE EF
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
L
H
H
0
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
IDT72V17320
0
0
(n+1) to 8,192
(n+1) to 32,768
8,193 to (16,384-(m+1))
32,769 to (65,536-(m+1))
(16,384-m) to 16,383
(65,536-m) to 65,535
16,384
65,536
IDT72V18320
IDT72V19160
Number of
Words in
FIFO
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
Number of
Words in
FIFO
IDT72V15320
IDT72V16320
IDT72V15160
IDT72V16160
IDT72V17160
0
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
IDT72V19320
1 to n
(1)
IDT72V18160
NOTE:
1. See Table 1 for values for n, m.
12
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
WCLK
RCLK
X
X
X
X
X
X
X
X
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1
X
SEN
1
1
1
X
X
X
0
No Operation
Write Memory
Read Memory
No Operation
Invalid Operation
Operation
Serial Flag Programming
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
6163 drw06
Invalid Operation
TABLE 3 -- FLAG OFFSET PROGRAMMING, STATE OF
LD AND
SEN AFTER MASTER RESET
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
D
n
by toggling
WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set
LD LOW
and deactivate
SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus t
PAF
,
PAE will be valid
after the next two rising RCLK edges plus t
PAE
plus t
SKEW2
.
Refer also to
LD Signal description for more information on flag offset
programming and state requirements for
LD and SEN pins
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT V-III and Vx-III can be configured during the Master Reset cycle
with either synchronous or asynchronous timing for
PAF and PAE flags by use
of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAE is asserted and updated on the rising edge of RCLK
only and not WCLK.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK.
PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK.
13
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
The
OE input is used to provide Asynchronous control of the three-state Qn
outputs.
READ ENABLE (
REN )
When Read Enable is LOW, data is loaded from the FIFO array into the
output register on the rising edge of every RCLK cycle if the device is not empty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q
0
-Q
n
maintain the previous data value.
Every word accessed at Q
n
, including the first word written to an empty FIFO,
must be requested using
REN. When the last word has been read from the FIFO,
the Empty Flag (
EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed,
EF will go HIGH
allowing a read to occur. The
EF flag is updated by two RCLK cycles + t
SKEW
after the valid WCLK cycle.
SERIAL ENABLE (
SEN )
The
SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset.
SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK.
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in both IDT.
Refer to LOAD (
LD) pin and section "Programming Flag Offsets" for more
information on offset programming.
OUTPUT ENABLE (
OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When
OE is HIGH, the output data bus (Q
n
) goes
into a high impedance state.
LOAD (
LD )
This is a dual purpose pin. During Master Reset, the state of the
LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the
PAE and PAF flags, along with the serial programming option for these offset
registers (see Table 3).
After Master Reset, the
LD pin is used in conjunction with the SEN pin to
activate the programming process of the flag offset values
PAE and PAF. Pulling
LD LOW will begin a serial loading of these offset values.
Depending on the default or serial programming option the state of
LD and
SEN have to be considered before and after master reset. Refer also to section
"Programming Flag Offsets" for more information on offset programming.
Programming offsets with default values: With the
LD pin together with
the FSEL0 and FSEL1 the user has the option to choose one of eight preset
values for both offset registers. During master reset the
LD pin can be either
HIGH or LOW depending on the selected value. After Master Reset,
LD must
be high and should not change state.
SEN should be high during and after
Master Reset and should not change state.
Serial programming of offset values: In order to select serial program-
ming the
LD pin has to be HIGH during master. Both, LD and SEN pin have
to toggle to LOW in order to initial the serial programming.
LD should be high
during normal FIFO operation.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Programmable
flag timing mode. If asynchronous
PAF/PAE configuration is selected (PFM,
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
0
- D
n
)
Data inputs for 16 or 32-bit wide data.
CONTROLS:
MASTER RESET (
MRS )
A Master Reset is accomplished whenever the
MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array.
PAE will go LOW, PAF will go HIGH, HF will go HIGH, EF
will go LOW and
FF will go HIGH.
SI is supposed to be LOW during master reset.
PFM control settings are defined during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place.
MRS
is asynchronous.
PARTIAL RESET (
PRS )
A Partial Reset is accomplished whenever the
PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array,
PAE goes LOW, PAF goes HIGH,
HF goes HIGH, FF will go HIGH and EF will go LOW. The output register is
initialized to all zeroes.
PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
SERIAL IN (SI)
At the time of Master Reset, SI must be LOW.
After Master Reset, SI acts as a serial input for loading
PAE and PAF offsets
into the programmable registers.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF,
PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating
HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
WRITE ENABLE (
WEN )
When the
WEN input is LOW, data may be loaded into the FIFO array on
the rising edge of every WCLK cycle if the device is not full. Data is stored in
the FIFO array sequentially and independently of any ongoing read operation.
When
WEN is HIGH, no new data is written in the FIFO array on each WCLK
cycle.
To prevent data overflow,
FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to
occur. The
FF is updated by two WCLK cycles + t
SKEW
after the RCLK cycle.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the
EF, PAE and HF flags will not
be updated. (Note that RCLK is only capable of updating the
HF flag to HIGH).
The Write and Read Clocks can be independent or coincident.
14
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
LOW during
MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the
PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
OUTPUTS:
FULL FLAG (
FF )
When the FIFO is full,
FF will go LOW, inhibiting further write operations.
When
FF is HIGH, the FIFO is not full. If no reads are performed after a reset
(either
MRS or PRS), FF will go LOW after D writes to the FIFO (D = total number
of words).
FF is synchronous and updated on the rising edge of WCLK. FF is a double
register-buffered output.
EMPTY FLAG (
EF )
When the FIFO is empty,
EF will go LOW, inhibiting further read operations.
When
EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK. EF is a double
register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF )
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after reset (
MRS),
PAF will go LOW after (D - m) words are written to the FIFO. (D=total number
of words, m = full offset value). The default setting for this value is stated in the
footnote of Table 1.
If asynchronous
PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous
PAF
configuration is selected, the
PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE )
The Programmable Almost-Empty flag (
PAE) will go LOW when the FIFO
reaches the almost-empty condition.
PAE will go LOW when there are n words
or less in the FIFO. The offset "n" is the empty offset value. The default setting
for this value is stated in the footnote of Table 1.
If asynchronous
PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous
PAE
configuration is selected, the
PAE is updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets
HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
If no reads are performed after reset (
MRS or PRS), HF will go LOW after
(D/2 + 1) writes to the FIFO, where D = total number of words available in the
FIFO.
Because
HF is updated by both RCLK and WCLK, it is considered
asynchronous.
DATA OUTPUTS (Q
0
-Q
n
)
(Q
0
-Qn) are data outputs for 16-bit or 32-bit wide data.
15
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
t
4
t
3
TDO
TDO
TDI/
TMS
TCK
TRST
t
DO
Notes to diagram:
t1 =
t
TCKLOW
t2 =
t
TCKHIGH
t3 =
t
TCKFALL
t4 = t
TCKRISE
t5 =
tRST
(reset pulse width)
t6 = tRSR (reset recovery)
6163 drw07
t
5
t
6
t
1
t
2
t
TCK
t
DH
t
DS
Figure 2. Standard JTAG Timing
Parameter
Symbol
Test
Conditions
Min.
Max. Units
JTAG Clock Input Period t
TCK
-
100
-
ns
JTAG Clock HIGH
t
TCKHIGH
-
40
-
ns
JTAG Clock Low
t
TCKLOW
-
40
-
ns
JTAG Clock Rise Time
t
TCKRISE
-
-
5
(1)
ns
JTAG Clock Fall Time
t
TCKFALL
-
-
5
(1)
ns
JTAG Reset
t
RST
-
50
-
ns
JTAG Reset Recovery
t
RSR
-
50
-
ns
(
V
CC
= 3.3V
5%; Tcase = 0C to +85C)
NOTE:
1. Guaranteed by design.
SYSTEM INTERFACE PARAMETERS
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
Parameter
Symbol
Test Conditions
Min.
Max.
Units
Data Output
t
DO
(1)
-
20
ns
Data Output Hold
t
DOH
(1)
0
-
ns
Data Input
t
DS
t
rise=3ns
10
-
ns
t
DH
t
fall=3ns
10
-
NOTE:
1. 50pf loading on external output signals.
JTAG
AC ELECTRICAL CHARACTERISTICS
16
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and
TRST) are provided to
support the JTAG boundary scan interface. The IDT72V14320/72V15320/
72V16320/72V17320/72V18320/72V19320 incorporates the necessary tap
controller and modified pad cells to implement the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 3. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI,
TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
T
A
P
TAP
Cont-
roller
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
clkDR, ShiftDR
UpdateDR
TDO
TDI
TMS
TCLK
TRST
clklR, ShiftlR
UpdatelR
Instruction Register
Instruction Decode
Control Signals
6163 drw08
17
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (
TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Figure 4. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
1
1
1
Capture-IR
0
Capture-DR
0
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
1
0
1
1
1
6163 drw09
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input = TMS
0
0
1
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by
TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be "01".
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the Pause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
18
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72V14320/72V15320/72V16320/72V17320/72V18320/
72V19320, the Part Number field contains the following values:
IDT72V14320/15320/16320/17320/18320/19320 JTAG Device Identification Register
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits)
Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex
Instruction
Function
Value
0x00
EXTEST
Select Boundary Scan Register
0x02
IDCODE
Select Chip Identification data register
0x01
SAMPLE/PRELOAD
Select Boundary Scan Register
0x03
HIGH-IMPEDANCE
JTAG
0x0F
BYPASS
Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IIDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional
TRST pin or by otherwise moving to the
Test-Logic-Reset state.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
Device
Part# Field
IDT72V14320
04E5
IDT72V15320
04E4
IDT72V16320
04E3
IDT72V17320
04E2
IDT72V18320
04E1
IDT72V19320
04E0
19
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
20
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
Figure 5. Master Reset Timing
6163 drw10
FSEL0,
FSEL1
SEN
t
RSF
t
RSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q
0
- Q
n
t
RSF
EF
FF
t
RSF
t
RSF
t
RSS
t
RSS
PFM
t
RSS
MRS
t
RSR
REN
t
RSS
SI
t
RSR
t
RSR
WEN
t
RSS
t
RSS
t
RS
LD
t
RSR
t
RSS
21
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
t
RS
PRS
t
RSR
REN
t
RSS
6163 drw11
t
RSR
WEN
SEN
t
RSF
t
RSF
OE = HIGH
OE = LOW
PAE
PAF,
HF
Q
0
- Q
n
t
RSF
EF
FF
t
RSF
t
RSF
t
RSS
t
RSS
Figure 6. Partial Reset Timing
22
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
n
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
t
SKEW1
(1)
6163 drw12
WCLK
NO WRITE
1
2
1
2
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
A
t
ENS
t
ENS
t
SKEW1
(1)
t
DS
t
A
D
X
t
DH
t
CLK
t
CLKH
t
CLKL
D
X
+1
t
WFF
t
DH
FF
NO OPERATION
RCLK
REN
6163 drw13
EF
t
CLK
t
CLKH
t
CLKL
t
ENH
t
REF
t
A
t
OLZ
t
OE
Q0 - Qn
OE
WCLK
(1)
t
SKEW1
WEN
D0 -
Dn
t
ENS
t
ENS
t
ENH
t
DS
t
DH
D
0
1
2
t
OLZ
NO OPERATION
LAST WORD
D
0
D
1
D
1
t
ENS
t
ENH
t
DS
t
DH
t
OHZ
LAST WORD
t
REF
t
ENH
t
ENS
t
A
t
A
t
REF
t
ENS
t
ENH
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH (after one WCLK cycle pus t
WFF
). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than t
SKEW1
, then the
FF deassertion may be delayed one extra WCLK cycle.
2.
LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH (after one RCLK cycle plus t
REF
). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than t
SKEW1
, then
EF deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH.
3. First data word latency = t
SKEW1
+ 1*T
RCLK
+ t
REF.
23
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
WCLK
SEN
SI
6163 drw20
t
ENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
t
ENH
BIT X
(1)
t
LDH
t
DH
t
LDH
WCLK
WEN
PAF
RCLK
(3)
t
PAFS
REN
6163 drw23
D - (m+1) words in FIFO
(2)
D - m words in FIFO
(2)
1
2
1
2
D-(m+1) words
in FIFO
(2)
t
PAFS
t
ENH
t
ENS
t
SKEW2
t
ENH
t
ENS
t
CLKL
t
CLKL
Figure 9. Serial Loading of Programmable Flag Registers
NOTE:
1. X = 9 for the IDT72V14320 (total of 20 bits), X = 10 for the IDT72V15320 (total of 22 bits), X = 11 for the IDT72V15160 and IDT72V16320 (total of 24 bits), X = 12 for the IDT72V16160,
and IDT72V17320 (total of 26 bits), X = 13 for the IDT72V17160 and IDT72V18320 (total of 28 bits), X = 14 for the IDT72V18160 and IDT72V19320 (total of 30 bits), X = 15 for the
IDT72V19160 (total of 32 bits).
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3. t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 10. Synchronous Programmable Almost-Full Flag Timing
24
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n words in FIFO
,
t
PAES
t
SKEW2
t
PAES
1
2
1
2
(2)
REN
6163 drw24
t
ENS
t
ENH
n+1 words in FIFO
n words in FIFO
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1)
words in FIFO
RCLK
t
PAFA
REN
6163 drw25
D - m words
in FIFO
D - (m + 1) words in FIFO
NOTES:
1. n =
PAE offset.
2. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus t
PAES
). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE deassertion may be delayed one extra RCLK cycle.
3.
PAE is asserted and updated on the rising edge of WCLK only.
4. Select this mode by setting PFM HIGH during Master Reset.
Figure 11. Synchronous Programmable Almost-Empty Flag Timing
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 12. Asynchronous Programmable Almost-Full Flag Timing
25
INDUSTRIAL
TEMPERATURE RANGE
IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
6163 drw27
t
CLKL
t
CLKH
D/2 words in FIFO
D/2 + 1 words in FIFO
D/2 words in FIFO
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAE
t
ENS
t
PAEA
n + 1 words in FIFO
n words in FIFO
RCLK
t
PAEA
REN
6163 drw26
n words in FIFO
NOTES:
1. n =
PAE offset.
2.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
3. Select this mode by setting PFM LOW during Master Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing
NOTES:
1. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
Figure 14. Half-Full Flag Timing
26
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ORDERING INFORMATION
Thin Plastic Quad Flatpack (TQFP, PN80-1, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1, Vx-III only)
Low Power
6163 drw05
PF
BB
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
I
Industrial (-40
C to +85C)
L
4,096 x 16
3.3V Multimedia FIFO, V-III
8,192 x 16
3.3V Multimedia FIFO, V-III
16,384 x 16
3.3V Multimedia FIFO, V-III
32,768 x 16
3.3V Multimedia FIFO, V-III
65,526 x 16
3.3V Multimedia FIFO, V-III
1,024 x 32
3.3V Multimedia FIFO, Vx-III
2,048 x 32
3.3V Multimedia FIFO, Vx-III
4,096 x 32
3.3V Multimedia FIFO, Vx-III
8,192 x 32
3.3V Multimedia FIFO, Vx-III
16,384 x 32
3.3V Multimedia FIFO, Vx-III
32,768 x 32
3.3V Multimedia FIFO, Vx-III
72V15160
72V16160
72V17160
72V18160
72V19160
72V14320
72V15320
72V16320
72V17320
72V18320
72V19320
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Industrial
10