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Электронный компонент: 72V3624

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2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4664/3
AUGUST 2001
3.3 VOLT CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT72V3624
IDT72V3634
IDT72V3644
1
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
.UNCTIONAL BLOCK DIAGRAM
.EATURES:




Memory storage capacity:
IDT72V3624256 x 36 x 2
IDT72V3634512 x 36 x 2
IDT72V36441,024 x 36 x 2




Clock frequencies up to 100 MHz (6.5ns access time)




Two independent clocked FIFOs buffering data in opposite
directions




Select IDT Standard timing (using
EFA, EFB, FFA, and FFB
flags functions) or First Word Fall Through Timing (using ORA,
ORB, IRA, and IRB flag functions)




Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)




Serial or parallel programming of partial flags




Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)




Big- or Little-Endian format for word and byte bus sizes




Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings




Mailbox bypass registers for each FIFO




Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)




Auto power down minimizes power dissipation




Available in space saving 128-pin Thin Quad Flatpack (TQFP)




Pin and functionally compatible version of the 5V operating
IDT723624/723634/723644




Industrial temperature range (40


C to +85


C) is available
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
R
A
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MRS1
Mail 2
Register
MBF2
CLKB
CSB
W
/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
MRS2
MBF1
FIFO1
FIFO2
10
EFB
/ORB
AEB
36
36
FFB
/IRB
AFB
B
0
-B
35
FFA
/IRA
AFA
SPM
FS0/SD
FS1/
SEN
A
0
-A
35
EFA
/ORA
AEA
4664 drw01
36
36
Output Bus-
Matching
Output
Register
PRS2
PRS1
Timing
Mode
FWFT
36
36
36
36
Input Bus-
Matching
2
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
PIN CON.IGURATION
TQFP (PK128-1, order code: PF)
TOP VIEW
W/
R
A
CLKB
4664 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/
FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PRS2
Vcc
B35
B34
B33
B32
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
Vcc
B15
B14
B13
B12
GND
B11
B10
CSA
FFA
/IRA
EFA
/ORA
PRS1
Vcc
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
GND
GND
FS1/
SEN
MRS2
MBB
MBF1
Vcc
AEB
AFB
EFB
/ORB
FFB
/IRB
GND
CSB
W
/RB
ENB
A9
A8
A7
A
6
G
N
D
A
5
A4
A3
SPM
Vcc
A2
A1
A0
GND
B0
B1
B2
B3
B
4
B
5
GND
B
6
Vcc
B7
B8
B
9
104
103
INDEX
SIZE
DESCRIPTION:
The IDT72V3624/72V3634/72V3644 are pin and functionally compatible
versions of the IDT723624/723634/723644, designed to run off a 3.3V supply
for exceptionally low-power consumption. These devices are monolithic, high-
speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory
which supports clock frequencies up to 100 MHz and has read access times as
fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs
on board each chip buffer data in opposite directions. FIFO data on Port B can
be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-
Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
3
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected Port B bus width.
Each Mailbox register has a flag (
MBF1 and MBF2) to signal when new mail
has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location of
the memory array, configures the FIFO for Big- or Little-Endian byte arrange-
ment and selects serial flag programming, parallel flag programming, or one of
three possible default flag offset settings, 8, 16 or 64. There are two Master Reset
pins,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first long-
word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation is required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).
The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB) and
a programmable Almost-Full flag (
AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory.
AFA and AFB indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA and AEB are two-
stage synchronized to the port clock that reads data from its array. Program-
mable offsets for
AEA, AEB, AFA and AFB are loaded in parallel using Port A
or in serial via the SD input. The Serial Programming Mode pin (
SPM) makes
this selection. Three default offset settings are also provided. The
AEA and AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFB threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3624/72V3634/72V3644 are characterized for operation from
0
C to 70
C. Industrial temperature range (-40
C to +85
C) is available. They
are fabricated using IDT's high speed, submicron CMOS technology.
4
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port A Almost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Empty Flag
less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B Almost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Empty Flag
less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A Almost-
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Full Flag
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB
Port B Almost-
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
Full Flag
FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0-B35
Port A Data
I/O
36-bit bidirectional data port for side B.
BE/
FWFT
Big-Endian/
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this
First Word
case, depending on the bus size, the most significant byte or word on Port A is read from Port B first
Fall Through
(A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian operation.
Select
In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or
written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on
FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has
been selected, the level on
FWFT must be static throughout device operation.
BM
Bus-Match
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
Select
LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
(Port B)
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous
or coincident to CLKB.
FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous
or coincident to CLKA.
FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition
of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
Select
outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The
Select
B0-B35 outputs are in the high-impedance state when
CSB is HIGH.
EFA/ORA
Port A Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFA function is selected. EFA indicates whether
Output Ready
or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the
Flag
presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA is synchronized to the LOW-to-
HIGH transition of CLKA.
EFB/ORB
Port B Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFB function is selected. EFB indicates whether
Output Ready
or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the
Flag
presence of valid data on the B0-B35 outputs, available for reading.
EFB/ORB is synchronized to the LOW-to-
HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FFA/IRA
Port A Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFA function is selected. FFA indicates
Input Ready
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates
Flag
whether or not there is space available for writing to the FIFO1 memory.
FFA/IRA is synchronized to the
LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFB function is selected. FFB indicates whether
Input Ready
or not the FIFO2 memory is full. In theFWFT mode, the IRB function is selected. IRB indicates whether or
Flag
not there is space available for writing to the FIFO2 memory.
FFB/IRB is synchronized to the LOW-to-HIGH
transition of CLKB.
5
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Symbol
Name
I/O
Description
FS1/
SEN Flag Offset Select 1/
I
FS1/
SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Serial Enable,
Reset, FS1/
SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of three preset values (8, 16, or 64),
FS0/SD
Flag Offset Select 0/
I
parallel load from Port A, and serial load.
Serial Data
When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous
to the LOW-to-HIGH transition of CLKA. When FS1/
SEN is LOW, a rising edge on CLKA load the bit present
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32
for the 72V3624, 36 for the 72V3634, and 40 for the 72V3644. The first bit write stores the Y-register (Y1)
MSB and the last bit write stores the X-register (X2) LSB.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
Select
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
Flag
the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial
Reset of FIFO1.
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the
Flag
mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial
Reset of FIFO2.
MRS1
FIFO1 Master
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Reset
Port B output register to all zeroes. A LOW-to-HIGH transition on
MRS1 selects the programming method (serial
or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions
of CLKB must occur while
MRS1 is LOW.
MRS2
FIFO2 Master
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the
Reset
Port A output register to all zeroes. A LOW-to-HIGH transition on
MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-
to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
MRS2 is LOW.
PRS1
FIFO1 Partial
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Reset
Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
PRS2
FIFO2 Partial
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port
Reset
A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement,
programming method (serial or parallel), and programmable flag settings are all retained.
SIZE
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation.
SPM
Serial Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming
Mode
or default offsets (8, 16, or 64).
W/
RA
Port-A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
Read Select
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port-B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of
Read Select
CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
6
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING .REE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
Symbol
Rating
Commercial
Unit
V
CC
Supply Voltage Range
0.5 to +4.6
V
V
I
(2)
Input Voltage Range
0.5 to V
CC
+0.5
V
V
O
(2)
Output Voltage Range
0.5 to V
CC
+0.5
V
I
IK
Input Clamp Current (V
I
< 0 or V
I
> V
CC
)
20
mA
I
OK
Output Clamp Current (V
O
= < 0 or V
O
> V
CC
)
50
mA
I
OUT
Continuous Output Current (V
O
= 0 to V
CC
)
50
mA
I
CC
Continuous Current Through V
CC
or GND
400
mA
T
STG
Storage Temperature Range
65 to 150
C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING .REE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
RECOMMENDED OPERATING CONDITIONS
NOTES:
1. For 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V; T
A
= 0
to +70
C; JEDEC JESD8-A compliant.
2. All typical values are at V
CC
= 3.3V, T
A
= 25
C.
3. For additional I
CC
information, see Figure 1, Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
).
4. Characterized values, not currently tested.
5. Industrial temperature range is available by special order.
NOTE:
1. For 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V; T
A
= 0
to +70
C; JEDEC JESD8-A compliant.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
(1)
Supply Voltage
3.0
3.3
3.6
V
V
IH
High-Level Input Voltage
2
--
V
CC
+0.5
V
V
IL
Low-Level Input Voltage
--
--
0.8
V
I
OH
High-Level Output Current
--
--
4
mA
I
OL
Low-Level Output Current
--
--
8
mA
T
A
Operating Temperature
0
--
70
C
IDT72V3624
IDT72V3634
IDT72V3644
Commercial
t
CLK
= 10
(1)
, 15ns
Symbol
Parameter
Test Conditions
Min.
Typ.
(2)
Max.
Unit
V
OH
Output Logic "1" Voltage
V
CC
= 3.0V,
I
OH
= 4 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage
V
CC
= 3.0V,
I
OL
= 8 mA
--
--
0.5
V
I
LI
Input Leakage Current (Any Input)
V
CC
= 3.6V,
V
I
= V
CC
or 0
--
--
10
A
I
LO
Output Leakage Current
V
CC
= 3.6V,
V
O
= V
CC
or 0
--
--
10
A
I
CC2
(3)
Standby Current (with CLKA and CLKB running)
V
CC
= 3.6V,
V
I
= V
CC
- 0.2V or 0
--
--
5
mA
I
CC3
(3)
Standby Current (no clocks running)
V
CC
= 3.6V,
V
I
= V
CC
- 0.2V or 0
--
--
1
mA
C
IN
(4)
Input Capacitance
V
I
= 0,
f = 1 MHz
--
4
--
pF
C
OUT
(4)
Output Capacitance
V
O
= 0,
f = 1 MHZ
--
8
--
pF
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The I
CC(f)
current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3624/72V3634/72V3644 with
CLKA and CLKB set to f
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With I
CC(f)
taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
P
T
= V
CC
x I
CC
(f) +
(C
L
x V
CC
2
x fo)
N
where:
N
=
number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
C
L
=
output capacitance load
f
o
=
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
)
0
10
20
30
40
50
60
70
0
25
50
75
100
125
150
V
CC
= 3.3V
f
S
Clock Frequency MHz
I
CC(f)
Supply Current mA
f
data
= 1/2 f
S
T
A
= 25
C
C
L
= 0 pF
V
CC
= 3.0V
V
CC
= 3.6V
4664 drw03
175
200
80
90
100
8
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE
IDT72V3624L10
(1)
IDT72V3624L15
IDT72V3634L10
(1)
IDT72V3634L15
IDT72V3644L10
(1)
IDT72V3644L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
f
S
Clock Frequency, CLKA or CLKB
--
100
--
66.7
MHz
t
CLK
Clock Cycle Time, CLKA or CLKB
10
--
15
--
ns
t
CLKH
Pulse Duration, CLKA or CLKB HIGH
4.5
--
6
--
ns
t
CLKL
Pulse Duration, CLKA and CLKB LOW
4.5
--
6
--
ns
t
DS
Setup Time, A0-A35 before CLKA
and B0-B35 before CLKB
3
--
4
--
ns
t
ENS1
Setup Time
CSA before CLKA
;
CSB before CLKB
4
--
4.5
--
ns
t
ENS2
Setup Time ENA, W/
RA and MBA before CLKA
; ENB,
W/RB and MBB
3
--
4.5
--
ns
before CLKB
t
RSTS
Setup Time,
MRS1, MRS2, PRS1, or PRS2 LOW before CLKA
or CLKB
(2)
5
--
5
--
ns
t
FSS
Setup Time, FS0 and FS1 before
MRS1 and MRS2 HIGH
7.5
--
7.5
--
ns
t
BES
Setup Time, BE/
FWFT before MRS1 and MRS2 HIGH
7.5
--
7.5
--
ns
t
SPMS
Setup Time,
SPM before MRS1 and MRS2 HIGH
7.5
--
7.5
--
ns
t
SDS
Setup Time, FS0/SD before CLKA
3
--
4
--
ns
t
SENS
Setup Time, FS1/
SEN before CLKA
3
--
4
--
ns
t
FWS
Setup Time, BE/
FWFT before CLKA
0
--
0
--
ns
t
DH
Hold Time, A0-A35 after CLKA
and B0-B35 after CLKB
0.5
--
1
--
ns
t
ENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
;
CSB, W/RB, ENB, and
0.5
--
1
--
ns
MBB after CLKB
t
RSTH
Hold Time,
MRS1, MRS2, PRS1 or PRS2 LOW after CLKA
or CLKB
(2)
4
--
4
--
ns
t
FSH
Hold Time, FS0 and FS1 after
MRS1 and MRS2 HIGH
2
--
2
--
ns
t
BEH
Hold Time, BE/
FWFT after MRS1 and MRS2 HIGH
2
--
2
--
ns
t
SPMH
Hold Time,
SPM after MRS1 and MRS2 HIGH
2
--
2
--
ns
t
SDH
Hold Time, FS0/SD after CLKA
0.5
--
1
--
ns
t
SENH
Hold Time, FS1/
SEN HIGH after CLKA
0.5
--
1
--
ns
t
SPH
Hold Time, FS1/
SEN HIGH after MRS1 and MRS2 HIGH
2
--
2
--
ns
t
SKEW1
(3)
Skew Time between CLKA
and CLKB
for
EFA/ORA, EFB/ORB, FFA/IRA,
5
--
7.5
--
ns
and
FFB/IRB
t
SKEW2
(3,4)
Skew Time between CLKA
and CLKB
for
AEA, AEB, AFA, and AFB
12
--
12
--
ns
NOTES:
1. For 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V; T
A
= 0
to +70
C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
Commercial: V
CC
= 3.3V +/- 0.30V; for 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V ; T
A
= 0
Cto +70
C; JEDEC JESD8-A compliant
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE, C
L
= 30p.
IDT72V3624L10
(1)
IDT72V3624L15
IDT72V3634L10
(1)
IDT72V3634L15
IDT72V3644L10
(1)
IDT72V3644L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
A
Access Time, CLKA
to A0-A35 and CLKB
to B0-B35
2
6.5
2
10
ns
t
WFF
Propagation Delay Time, CLKA
to
FFA/IRA and CLKB
to
FFB/IRB
2
6.5
2
8
ns
t
REF
Propagation Delay Time, CLKA
to
EFA/ORA and CLKB
to
EFB/ORB
1
6.5
1
8
ns
t
PAE
Propagation Delay Time, CLKA
to
AEA and CLKB
to
AEB
1
6.5
1
8
ns
t
PAF
Propagation Delay Time, CLKA
to
AFA and CLKB
to
AFB
1
6.5
1
8
ns
t
PMF
Propagation Delay Time, CLKA
to
MBF1 LOW or MBF2 HIGH and CLKB
0
6.5
0
8
ns
to
MBF2 LOW or MBF1 HIGH
t
PMR
Propagation Delay Time, CLKA
to B0-B35
(2)
and CLKB
to A0-A35
(3)
2
8
2
10
ns
t
MDV
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid
2
6.5
2
10
ns
t
RSF
Propagation Delay Time,
MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and
1
10
1
15
ns
MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2
HIGH
t
EN
Enable Time,
CSA or W/RA LOW to A0-A35 Active and CSB LOW and W/RB
2
6
2
10
ns
HIGH to B0-B35 Active
t
DIS
Disable Time,
CSA or W/RA HIGH to A0-A35 at high-impedance and CSB
1
6
1
8
ns
HIGH or
W/RB LOW to B0-B35 at HIGH impedance
NOTES:
1. For 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V; T
A
= 0
to +70
C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
Commercial: V
CC
= 3.3V +/- 0.30V; for 10ns (100 MHz operation), V
CC
= 3.3V +/- 0.15V ; T
A
= 0
C to +70
C; JEDEC JESD8-A compliant
10
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1, MRS2)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1 and MRS2 simultaneously. Afterwards, each of the two
FIFO memories of the IDT72V3624/72V3634/72V3644 undergoes a complete
reset by taking its associated Master Reset (
MRS1, MRS2) input LOW for at
least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH
transitions. The Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the associated write and read pointers to the first
location of the memory and forces the Full/Input Ready flag (
FFA/IRA, FFB/
IRB) LOW, the Empty/Output Ready flag (
EFA/ORA, EFB/ORB) LOW, the
Almost-Empty flag (
AEA, AEB) LOW and forces the Almost-Full flag (AFA, AFB)
HIGH. A Master Reset also forces the associated Mailbox Flag (
MBF1, MFB2)
of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/
Input Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready
to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (
MRS1) input
latches the values of the Big-Endian (BE) input for determining the order by
which bytes are transferred through Port B. It also latches the values of the
Flag Select (FS0, FS1) and Serial Programming Mode (
SPM) inputs for
choosing the Almost-Full and Almost-Empty offset programming method.
A LOW-to-HIGH transition on the FIFO2 Master Reset (
MRS2) clears the
Flag Offset Registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the
FIFO2 Master Reset (
MRS2) together with the FIFO1 Master Reset (MRS1)
input latches the value of the Big-Endian (BE) input for Port B and also latches
the values of the Flag Select (FS0, FS1) and Serial Programming Mode (
SPM)
inputs for choosing the Almost-Full and Almost-Empty offset programming
method. (For details see Table 1, Flag Programming, and the Programming
the Almost-Empty and Almost-Full Flags
section). The relevant FIFO Master
Reset timing diagram can be found in Figure 3.
PARTIAL RESET (
PRS1, PRS2)
Each of the two FIFO memories of these devices undergoes a limited reset
by taking its associated Partial Reset (
PRS1, PRS2) input LOW for at least four
Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial
Reset initializes the internal read and write pointers and forces the Full/Input
Ready flag (
FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/
ORA,
EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the
Almost-Full flag (
AFA, AFB) HIGH. A Partial Reset also forces the Mailbox Flag
(
MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the
FIFO's Full/Input Ready flag is set HIGH after two write clock cycles. Then
the FIFO is ready to be written to.
Whatever flag offsets, programming method (parallel or serial), and timing
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be inconvenient. See
Figure 4 for the Partial Reset timing diagram.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT)
-- ENDIAN SELECTION
This is a dual purpose pin. At the time of Master Reset, the BE select function
is active, permitting a choice of Big or Little-Endian byte arrangement for data
written to or read from Port B. This selection determines the order by which bytes
(or words) of data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been selected for Port
B. (Note that when Port B is configured for a long word size, the Big-Endian
function has no application and the BE input is a "don't care"
1
.)
A HIGH on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputs go from LOW to HIGH will select a Big-Endian arrangement. When data
is moving in the direction from Port A to Port B, the most significant byte (word)
of the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFT input when the Master Reset (MRS1, MRS2)
inputs go from LOW to HIGH will select a Little-Endian arrangement. When data
is moving in the direction from Port A to Port B, the least significant byte (word)
of the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port B to Port A, the byte (word) written to
Port B first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port B last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 for an illustration of
the BE function. See Figure 3 (Master Reset) for the Endian select timing
diagram.
-- TIMING MODE SELECTION
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (
MRS1, MRS2) input is HIGH,
a HIGH on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (
EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (
FFA,
FFB) to indicate whether or not the FIFO memory has any free space for writing.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
Once the Master Reset (
MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/
FWFT input to choose
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in the IDT72V3624/72V3634/72V3644 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (
AEB) Offset register is labeled X1 and the Port A Almost-Empty flag
(
AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset
register is labeled Y1 and the Port B Almost-Full flag (
AFB) Offset register is
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
11
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SPM
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS
(1)
X2 AND Y2 REGlSTERS
(2)
H
H
H
X
64
X
H
H
H
64
64
H
H
L
X
16
X
H
H
L
16
16
H
L
H
X
8
X
H
L
H
8
8
H
L
L
Parallel programming via Port A
Parallel programming via Port A
L
H
L
Serial programming via SD
Serial programming via SD
L
H
H
Reserved
Reserved
L
L
H
Reserved
Reserved
L
L
L
Reserved
Reserved
labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO's Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
SPM, FS0/SD, and FS1/SEN function the same way in both IDT Standard
and FWFT modes.
-- PRESET VALUES
To load a FIFO's Almost-Empty flag and Almost-Full flag Offset registers with
one of the three preset values listed in Table 1, the Serial Program Mode (
SPM)
and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (
MRS1, MRS2). For example, to load the
preset value of 64 into X1 and Y1,
SPM, FS0 and FS1 must be HIGH when
FlFO1 reset (
MRS1) returns HIGH. Flag-offset registers associated with FIFO2
are loaded with one of the preset values in the same way with FIFO2 Master
Reset (
MRS2), toggled simultaneously with FIFO1 Master Reset (MRS1). For
relevant preset value loading timing diagram, see Figure 3.
-- PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with
SPM HIGH and FS0 and FS1 LOW
during the LOW-to-HIGH transition of
MRS1 and MRS2. After this reset is
complete, the first four writes to FIFO1 do not store data in the RAM but load
the offset registers in the order Y1, X1, Y2, X2. The Port A data inputs used by
the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The highest numbered input is
used as the most significant bit of the binary number in each case. Valid
programming values for the registers range from 1 to 252 for the IDT72V3624;
1 to 508 for the IDT72V3634; and 1 to 1,020 for the IDT72V3644. After all the
offset registers are programmed from Port A, the Port B Full/Input Ready flag
(
FFB/IRB) is set HIGH, and both FIFOs begin normal operation. Refer to Figure
5 for a timing diagram illustration of parallel programming of the flag offset values.
-- SERIAL LOAD
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
with
SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
transition of
MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/
SEN input is LOW. There are 32-, 36-, or 40-
bit writes needed to complete the programming for the IDT72V3624,
IDT72V3634, or IDT72V3644, respectively. The four registers are written in
the order Y1, X1, Y2, and finally, X2. The first-bit write stores the most significant
bit of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from 1 to 252 (IDT72V3624),
1 to 508 (IDT72V3634), or 1 to 1,020 (IDT72V3644).
When the option to program the offset registers serially is chosen, the Port
A Full/Input Ready (
FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFB/
IRB) flag also remains LOW throughout the serial programming process, until
all register bits are written.
FFB/IRB is set HIGH by the LOW-to-HIGH transition
of CLKB after the last bit is loaded to allow normal FIFO2 operation. See Figure
6 for Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (IDT Standard and FWFT Modes)
timing diagram.
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
(
CSA) and Port A Write/Read select (W/RA). The A0-A35 lines are in the High-
impedance state when either
CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and
EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B operation.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (
W/RB) is the inverse of the Port A Write/Read
select (W/
RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (
CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either
CSB is HIGH or W/RB is
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
TABLE 1 .LAG PROGRAMMING
12
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
TABLE 3 PORT B ENABLE .UNCTION TABLE
LOW. The B0-B35 lines are active outputs when
CSB is LOW and W/RB is
HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and
FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
by a LOW-to-HIGH transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB
is HIGH, MBB is LOW, and
EFB/ORB is HIGH (see Table 3). FIFO reads and
writes on Port B are independent of any concurrent Port A operation.
The setup and hold time constraints to the port clocks for the port Chip Selects
and Write/Read selects are only for enabling write and read operations and
are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port's Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO's output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port's Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port's Chip Select, Write/Read
select, Enable, and Mailbox select. Write and read timing diagrams for Port A
can be found in Figure 7 and 14. Relevant Port B write and read cycle timing
diagrams together with Bus-Matching and Endian select operations can be
found in Figures 8 through 13.
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
X
X
X
High-Impedance
None
L
H
L
X
X
Input
None
L
H
H
L
Input
FIFO1 write
L
H
H
H
Input
Mail1 write
L
L
L
L
X
Output
None
L
L
H
L
Output
FIFO2 read
L
L
L
H
X
Output
None
L
L
H
H
Output
Mail2 read (set
MBF2 HIGH)
TABLE 2 PORT A ENABLE .UNCTION TABLE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
X
X
X
X
High-Impedance
None
L
L
L
X
X
Input
None
L
L
H
L
Input
FIFO2 write
L
L
H
H
Input
Mail2 write
L
H
L
L
X
Output
None
L
H
H
L
Output
FIFO1 read
L
H
L
H
X
Output
None
L
H
H
H
Output
Mail1 read (set
MBF1 HIGH)
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another.
EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and
5 show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready
(ORA, ORB) function is selected. When the Output-Ready flag is HIGH, new
data is present in the FIFO output register. When the Output Ready flag is LOW,
the previous data word is present in the FIFO output register and attempted
FIFO reads are ignored.
13
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Synchronized
Synchronized
Number of Words in FIFO Memory
(1,2)
to CLKA
to CLKB
IDT72V3624
(3)
IDT72V3634
(3)
IDT72V3644
(3)
EFA/ORA
AEA
AFB
FFB/IRB
0
0
0
L
L
H
H
1 to X2
1 to X2
1 to X2
H
L
H
H
(X2+1) to [256-(Y2+1)]
(X2+1) to [512-(Y2+1)]
(X2+1) to [1,024-(Y2+1)]
H
H
H
H
(256-Y2) to 255
(512-Y2) to 511
(1,024-Y2) to 1,023
H
H
L
H
256
512
1,024
H
H
L
L
TABLE 4 .I.O1 .LAG OPERATION (IDT Standard and .W.T modes)
TABLE 5 .I.O2 .LAG OPERATION (IDT Standard and .W.T modes)
Synchronized
Synchronized
Number of Words in FIFO Memory
(1,2)
to CLKB
to CLKA
IDT72V3624
(3)
IDT72V3634
(3)
IDT72V3644
(3)
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 to X1
1 to X1
1 to X1
H
L
H
H
(X1+1) to [256-(Y1+1)]
(X1+1) to [512-(Y1+1)]
(X1+1) to [1,024-(Y1+1)]
H
H
H
H
(256-Y1) to 255
(512-Y1) to 511
(1,024-Y1) to 1,023
H
H
L
H
256
512
1,024
H
H
L
L
In the IDT Standard mode, the Empty Flag (
EFA, EFB) function is selected.
When the Empty Flag is HIGH, data is available in the FIFO's RAM memory
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a minimum of
two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag
is LOW if a word in memory is the next data to be sent to the FlFO output register
and two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 15, 16, 17, and 18).
FULL/INPUT READY FLAGS (
FFA/IRA, FFB/IRB)
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
function is selected. In IDT Standard mode, the Full Flag (
FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by
AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by
AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRB functions are active during FWFT mode; the
EFA and FFB functions are active in IDT Standard mode.
14
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time t
SKEW1
or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).
ALMOST-EMPTY FLAGS (
AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for
AEB and
register X2 for
AEA. These registers are loaded with preset values during a
FIFO reset, programmed from Port A, or programmed serially (see Almost-
Empty flag and Almost-Full flag offset programming
section). An Almost-
Empty flag is LOW when its FIFO contains X or less words and is HIGH when
its FIFO contains (X+1) or more words. A data word present in the FIFO output
register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since
the write that filled the memory to the (X+1) level. An Almost-Empty flag is set
HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycle if it occurs at time t
SKEW2
or greater after the write that fills the FIFO to (X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figure 23 and 24).
ALMOST-FULL FLAGS (
AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state
is defined by the contents of register Y1 for
AFA and register Y2 for AFB. These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming
section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y)
for the IDT72V3624, IDT72V3634, or IDT72V3644 respectively. An Almost-
Full flag is HIGH when the number of words in its FIFO is less than or equal
to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT72V3624,
IDT72V3634, or IDT72V3644 respectively. Note that a data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for its Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
[256/512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that reduces
the number of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time
t
SKEW2
or greater after the read that reduces
the number of words in memory to [256/512/1,024-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 25 and 26).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between Port A and Port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port data transfer operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes data to the Mail 1 Register when
a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If the
selected Port B bus size is also 36 bits, then the usable width of the Mail1 register
employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail1 Register employs data lines A0-A17. (In this case,
A18-A35 are don't care inputs.) If the selected Port B bus size is 9 bits, then
the usable width of the Mail1 Register employs data lines A0-A8. (In this case,
A9-A35 are don't care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by
CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is also 36 bits, then the usable width of
the Mail2 employs data lines B0-B35. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines B0-B17. (In this
case, B18-B35 are don't care inputs.) If the selected Port B bus size is 9 bits,
then the usable width of the Mail2 Register employs data lines B0-B8. (In this
case, B9-B35 are don't care inputs.)
Writing data to a mail register sets its corresponding flag (
MBF1 or MBF2)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port Mailbox select input is HIGH.
The Mail1 Register Flag (
MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
The Mail2 Register Flag (
MBF2) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian select feature has no effect
on mailbox data. For mail register and Mail Register Flag timing diagrams, see
Figure 27 and 28.
15
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bit byte format for data read from FIFO1 or written to FIFO2. The levels
applied to the Port B Bus Size select (SIZE) and the Bus-Match select (BM)
determine the Port B bus size. These levels should be static throughout FIFO
operation. Both bus size selections are implemented at the completion of Master
Reset, by the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Two different methods for sequencing data transfer are available for Port
B when the bus size selection is either byte- or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
byte first). The level applied to the Big-Endian select (BE) input during the LOW-
to-HIGH transition of
MRS1 and MRS2 selects the endian method that will be
active during FIFO operation. BE is a don't care input when the bus size
selected for Port B is long word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready flag is set HIGH,
as shown in Figure 2.
Only 36-bit long word data is written to or read from the two FIFO memories
on the IDT72V3624/72V3634/72V3644. Bus-matching operations are done
after data is read from the FIFO1 RAM and before data is written to the FIFO2
RAM. These bus-matching operations are not available when transferring
data via mailbox registers. Furthermore, both the word- and byte-size bus
selections limit the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the selected word-
or byte-size bus can carry mailbox data. The remaining data outputs will be
indeterminate. The remaining data inputs will be don't care inputs. For
example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 27 and 28).
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the
FIFO1 output register. If byte or word size is implemented on Port B, only the
first one or two bytes appear on the selected portion of the FIFO1 output register,
with the rest of the long word stored in auxiliary registers. In this case,
subsequent FIFO1 reads output the rest of the long word to the FIFO1 output
register in the order shown by Figure 2.
When reading data from FIFO1 in byte or word format, the unused B0-B35
outputs are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data written
to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary
registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 2.
When writing data to FIFO2 in byte or word format, the unused B0-B35 inputs
are don't care inputs.
16
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 2. Bus Sizing
A35 A27 A26 A18 A17 A9 A8 A0
B35 B27 B26 B18 B17 B9 B8 B0
A
A
A
D
A
C
B
B
B
C
B
D
C
C
C
A
D
D
D
B
(a) LONG WORD SIZE
(b) WORD SIZE BIG ENDIAN
(c) WORD SIZE LITTLE-ENDIAN
(d) BYTE SIZE BIG-ENDIAN
Write to FIFO1/
Read from FIFO2
Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
BE BM SIZE
H H L
L H L
H H H
X L X
BYTE ORDER ON PORT A:
BE BM SIZE
BE BM SIZE
BE BM SIZE
2nd: Read from FIFO1/
Write to FIFO2
3rd: Read from FIFO1/
Write to FIFO2
4th: Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
D
C
(e) BYTE SIZE LITTLE-ENDIAN
1st: Read from FIFO1/
Write to FIFO2
A
B
BE BM SIZE
L H H
2nd: Read from FIFO1/
Write to FIFO2
3rd: Read from FIFO1/
Write to FIFO2
4th: Read from FIFO1/
Write to FIFO2
4664 drw04
BYTE ORDER ON PORT B:
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
B35 B27 B26 B18 B17 B9 B8 B0
17
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. Partial Reset is performed in the same manner for FIFO2.
2.
MRS1 must be HIGH during Partial Reset.
3. If BE/
FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight
(1)
(IDT Standard and FWFT Modes)
Figure 4. FIFO1 Partial Reset
(1)
(IDT Standard and FWFT Modes)
NOTES:
1. FIFO2 Master Reset (
MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.
2.
PRS1 must be HIGH during Master Reset.
3. If BE/
FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
CLKA
MRS1
FFA
/IRA
AEB
AFA
MBF1
CLKB
EFB
/ORB
FS1,FS0
4664 drw05
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
WFF
t
REF
t
RSF
0,1
t
RSF
t
RSF
BE
BE/
FWFT
SPM
FWFT
t
BES
t
SPMS
t
BEH
t
SPMH
t
FWS
(3)
CLKA
PRS1
FFA
/IRA
AEB
AFA
MBF1
CLKB
EFB
/ORB
4664 drw06
t
RSTS
t
RSTH
t
REF(3)
t
RSF
t
RSF
t
RSF
t
WFF
t
WFF
18
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
NOTES:
1. t
SKEW1
is the minimum time between the rising CLKA edge and a rising CLKB edge for
FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than t
SKEW1
, then
FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until
FFA/IRA and FFB/IRB is set HIGH.
3. Programmable offsets are written serially to the SD input in the order
AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
NOTES:
1. t
SKEW1
is the minimum time between the rising CLKA edge and a rising CLKB edge for
FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than t
SKEW1
, then
FFB/IRB may transition HIGH one CLKB cycle later than shown.
2.
CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
4664 drw07
CLKA
MRS1
,
MRS2
FFA
/IRA
CLKB
FFB
/IRB
A0-A35
FS1,FS0
ENA
t
FSH
t
WFF
t
ENH
t
ENS2
t
SKEW1
t
DS
t
DH
t
WFF
4
0,0
AFA
Offset
(Y1)
AEB
Offset
(X1)
AFB
Offset
(Y 2)
AEA
Offset
(X 2)
First Word to FIFO1
1
2
(1)
t
FSH
t
FSS
SPM
t
FSS
1
2
CLKA
FFA
/IRA
t
SENS
t
SENH
FS0/SD(3)
t
SPH
t
SENS
t
SENH
t
FSS
t
WFF
FS1/
SEN
AEA
Offset (X2) LSB
t
SDS
t
SDH
t
SDS
t
SDH
AFA
Offset (Y1) MSB
MRS1
,
MRS2
4
4664 drw08
t
FSS
t
FSH
CLKB
4
SPM
FFB
/IRB
t
WFF
t
SKEW(1)
19
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTE:
1. Written to FIFO1.
Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
DATA SIZE TABLE .OR LONG-WORD WRITES TO .I.O2
Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
SIZE MODE
(1)
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
BM
SIZE
BE
B35-B27
B26-B18
B17-B9
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.
NOTE:
1. Written to FIFO2.
4664 drw09
CLKA
FFA
/IRA
ENA
A0 - A35
MBA
CSA
W/
R
A
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
ENS2
t
ENH
t
ENH
t
ENS2
No Operation
HIGH
4664 drw10
CLKB
FFB
/IRB
ENB
B0-B35
MBB
CSB
W
/RB
t
CLK
t
CLKH
t
CLKL
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
DS
t
ENH
t
ENH
t
ENS2
No Operation
HIGH
t
ENS2
t
ENS2
t
ENS2
t
ENS2
t
ENS1
20
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIZE MODE
(1)
WRITE
DATA WRITTEN
DATA READ FROM FIFO2
NO.
TO FIFO2
BM
SIZE
BE
B17-B9
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
H
L
H
A
B
C
D
H
L
L
A
B
C
D
DATA SIZE TABLE .OR WORD WRITES TO .I.O2
1
A
B
2
C
D
1
C
D
2
A
B
Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
SIZE MODE
(1)
WRITE
DATA WRITTEN
DATA READ FROM FIFO2
NO.
TO FIFO2
BM
SIZE
BE
B8-B0
A35-A27
A26-A18
A17-A9
A8-A0
H
H
H
A
B
C
D
H
H
L
A
B
C
D
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
DATA SIZE TABLE .OR BYTE WRITES TO .I.O2
Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
CLKB
ENB
t
ENH
t
ENH
FFB
/IRB
W
/RB
CSB
t
ENH
HIGH
4664 drw11
B0-B17
t
ENH
t
ENH
MBB
t
DH
t
DS
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
ENS2
t
ENS2
FFB
/IRB
CSB
W
/RB
CLKB
t
ENH
t
ENS2
ENB
4664 drw12
HIGH
B0-B8
t
ENS2
t
ENH
t
ENS2
t
ENH
t
DS
t
DH
t
ENS2
t
ENS1
t
ENH
t
ENH
MBB
21
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SIZE MODE
(1)
DATA WRITTEN TO FIFO1
READ NO. DATA READ FROM FIFO1
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B17-B9
B8-B0
H
L
H
A
B
C
D
1
A
B
2
C
D
H
L
L
A
B
C
D
1
C
D
2
A
B
DATA SIZE TABLE .OR WORD READS .ROM .I.O1
Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
SIZE MODE
(1)
DATA WRITTEN TO FIFO1
DATA READ FROM FIFO1
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. Read From FIFO1.
DATA SIZE TABLE .OR .I.O LONG-WORD READS .ROM .I.O1
Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
NOTE:
1. Unused word B18-B35 are indeterminate for word-size reads.
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .
4664 drw13
CLKB
EFB
/ORB
ENB
MBB
CSB
W
/RB
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
W1
W2
W3
(1)
(1)
t
ENH
t
DIS
No Operation
B0-B35
(FWFT Mode)
t
EN
W2
(1)
t
DIS
W1
Previous Data
B0-B35
(Standard Mode)
t
MDV
t
A
OR
t
A
HIGH
t
ENS2
t
ENS2
t
ENS2
(1)
(1)
CLKB
ENB
EFB
/ORB
W
/RB
CSB
HIGH
4664 drw14
B0-B17
(Standard Mode)
B0-B17
(FWFT Mode)
OR
Previous Data
t
A
t
A
t
ENS2
t
ENH
No Operation
Read 1
t
A
t
A
Read 1
Read 2
Read 2
Read 3
MBB
t
EN
t
MDV
t
EN
t
MDV
t
DIS
t
DIS
22
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
EFB
/ORB
MBB
CSB
W
/RB
ENB
CLKB
HIGH
B0-B8
B0-B8
Read 5
Read 2
Read 3
Read 4
Read 3
Read 4
Previous Data
Read 2
No Operation
t
DIS
t
DIS
t
A
t
A
t
A
t
A
t
A
t
A
t
ENS2
t
ENH
t
A
t
A
Read 1
(Standard Mode)
(FWFT Mode)
t
EN
t
MDV
t
MDV
t
EN
OR
Read 1
4664 drw15
DATA SIZE TABLE .OR BYTE READS .ROM .I.O1
SIZE MODE
(1)
DATA WRITTEN TO FIFO1
READ
DATA READ
NO.
FROM FIFO1
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B8-B0
H
H
H
A
B
C
D
H
H
L
A
B
C
D
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.
NOTE:
1. Read From FIFO2.
4664 drw16
CLKA
EFA
/ORA
ENA
MBA
CSA
W/
R
A
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
W1
W2
W3
(1)
(1)
t
ENH
t
DIS
No Operation
A0-A35
(FWFT Mode)
t
EN
W2
(1)
(1)
t
DIS
W1
Previous Data
A0-A35
(Standard Mode)
t
MDV
t
A
OR
t
A
HIGH
t
ENS2
t
ENS2
t
ENS2
(1)
23
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CSA
W/
R
A
MBA
IRA
A0-A35
CLKB
ORB
CSB
W
/RB
MBB
ENA
ENB
B0-B35
CLKA
4664 drw17
1
2
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLKL
t
REF
t
REF
t
ENS2
t
ENH
t
A
Old Data in FIFO1 Output Register
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
t
CLK
24
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then the transition of
EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte,
EFB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 16.
EFB
Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
CSA
W/
R
A
MBA
FFA
A0-A35
CLKB
EFB
CSB
W
/RB
MBB
ENA
ENB
B0-B35
CLKA
1
2
4664 drw18
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS2
t
ENH
t
A
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
t
REF
t
REF
25
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKB edge and the rising CLKA edge is less than t
SKEW1
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port B size is word or byte, t
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
CSB
W
/RB
MBB
IRB
B0-B35
CLKA
ORA
CSA
W/
R
A
MBA
ENB
ENA
A0-A35
CLKB
4664 drw19
1
2
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
(1)
t
CLK
t
CLKH
t
REF
t
REF
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output Register
W1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
26
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then the transition of
EFA HIGH may occur one CLKA cycle later than shown.
2. If Port B size is word or byte, t
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte
of the long word, respectively.
Figure 18.
EFA
Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
CSB
W
/RB
MBB
FFB
B0-B35
CLKA
EFA
CSA
W/
R
A
MBA
ENB
ENA
A0-A35
CLKB
1
2
4664 drw20
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
(1)
t
CLK
t
CLKL
t
ENS2
t
ENH
t
A
W1
FIFO2 Empty
LOW
LOW
LOW
LOW
LOW
t
CLKH
W1
HIGH
t
REF
t
REF
27
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 20.
FFA
Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then
FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, t
SKEW1
is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, t
SKEW1
is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
CSB
ORB
W
/RB
MBB
ENB
B0-B35
CLKB
IRA
CLKA
CSA
4664 drw21
W/
R
A
A0-A35
MBA
ENA
1
2
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
WFF
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
Write
CSB
EFB
MBB
ENB
B0-B35
CLKB
FFA
CLKA
CSA
4664 drw22
W/
R
A
1
2
A0-A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W
/RB
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
t
WFF
Write
t
ENS2
t
ENS2
t
ENS2
28
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then IRB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CSA
ORA
W/
R
A
MBA
ENA
A0-A35
CLKA
IRB
CLKB
CSB
4664 drw23
W
/RB
B0-B35
MBB
ENB
1
2
t
CLK
t
CLKH
t
CLKL
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
WFF
t
WFF
t
ENH
t
ENH
t
DS
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
FIFO2 FULL
LOW
LOW
LOW
HIGH
LOW
LOW
(1)
Write
t
ENS2
t
ENS2
t
ENS2
29
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 22.
FFB
Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
NOTES:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then
FFB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte,
FFB is set LOW by the last word or byte write of the long word, respectively.
CSA
EFA
MBA
ENA
A0-A35
CLKA
FFB
CLKB
CSB
4664 drw24
W
/RB
1
2
B0-B35
MBB
ENB
t
CLK
t
CLKH
t
CLKL
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/
R
A
LOW
LOW
HIGH
LOW
LOW
(1)
FIFO2 Full
t
WFF
t
WFF
Write
t
ENS2
t
ENS2
30
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 25. Timing for
AFA
when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
Figure 23. Timing for
AEB
when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 24. Timing for
AEA
when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW2
, then
AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte,
AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW2
, then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, t
SKEW2
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW2
, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte, t
SKEW2
is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
AEB
CLKA
ENB
4664 drw25
ENA
CLKB
2
1
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENH
X1 Words in FIFO1
(X1+1) Words in FIFO1
(1)
t
ENS2
t
ENS2
AEA
CLKB
ENA
4664 drw26
ENB
CLKA
2
1
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
t
ENS2
t
ENS2
AFA
CLKA
ENB
4664 drw27
ENA
CLKB
1
2
t
SKEW2
t
ENH
t
PAF
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
t
ENS2
t
ENS2
31
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 26. Timing for
AFB
when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 27. Timing for Mail1 Register and
MBF1
Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data
(B9-B35 will be indeterminate).
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW2
, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte,
AFB is set LOW by the last word or byte write of the long word, respectively.
AFB
CLKB
ENA
4664 drw28
ENB
CLKA
1
2
t
SKEW2
t
ENH
t
PAF
t
ENH
t
PAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)
t
ENS2
t
ENS2
4664 drw29
CLKA
ENA
A0-A35
MBA
CSA
W/
R
A
CLKB
MBF1
CSB
MBB
ENB
B0-B35
W
/RB
W1
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
t
ENH
t
ENH
t
ENH
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
ENS2
32
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 28. Timing for Mail2 Register and
MBF2
Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data
(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this
second case, A0-A8 will have valid data (A9-A35 will be indeterminate).
4664 drw30
CLKB
ENB
B0-B35
MBB
CSB
W
/RB
CLKA
MBF2
CSA
MBA
ENA
A0-A35
W/
R
A
W1
t
ENH
t
DH
t
PMF
t
PMF
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO2 Output Register
W1 (Remains valid in Mail 2 Register after read)
t
ENH
t
ENH
t
ENH
t
DS
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
ENS2
33
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Figure 29. Output Load and AC Test Conditions
NOTE:
1. Includes probe and jig capacitance.
4664 drw31
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
330
3.3V
510
PROPAGATION DELAY
LOAD CIRCUIT
3V
GND
Timing
Input
Data,
Enable
Input
GND
3V
1.5V
1.5V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3V
GND
GND
3V
1.5V
1.5V
1.5V
1.5V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3V
OL
GND
3V
1.5V
1.5V
1.5V
1.5V
OH
OV
GND
OH
OL
1.5V
1.5V
1.5V
1.5V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5V
3V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
34
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975 Stender Way
800-345-7015 or 408-727-6116
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
FIFOhelp@idt.com
www.idt.com
ORDERING IN.ORMATION
NOTE:
1. Industrial temperature range is available by special order.
BLANK
PF
L
72V3624
72V3634
72V3644
4664 drw32
Commercial (0
C to +70
C)
Thin Quad Flat Pack (TQFP, PK128-1)
Low Power
256 x 36 x 2
3.3V SyncBiFIFO
with Bus-Matching
512 x 36 x 2
3.3V SyncBiFIFO
with Bus-Matching
1,024 x 36 x 2
3.3V SyncBiFIFO
with Bus-Matching
XXXXXX
IDT
Device Type
X
XX
X
X
Power
Speed
Package
Process/
Temperature
Range
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Commercial Only
10
15
DATASHEET DOCUMENT HISTORY
12/12/2000
pg. 12.
03/21/2001
pgs. 6 and 7.
08/01/2001
pgs. 6, 8, 9 and 34.