1999 Integrated Device Technology, Inc.

DSC-3966/-

August 1999

IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9

FEATURES:

The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs

The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs

The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs

The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs

The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs

Low power consumption
-- Active: 330 mW (max.)
-- Power-down: 18 mW (max.)

Ultra high speed--15 ns access time

Asynchronous and simultaneous read and write

Offers optimal combination of data capacity, small foot print
and functional flexibility

Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications

Status Flags: Empty, Half-Full, Full

Auto-retransmit capability

High-performance CEMOSTM technology

Space-saving TSSOP package

Industrial temperature range (40

°°
°°
°

C to +85

°°
°°
°

C) is available

DESCRIPTION:

The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that

load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.

The reads and writes are internally sequential through the use of ring

pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (

W) and Read

(

R) pins.

The devices utilize a 9-bit wide data array to allow for control and parity

bits at the user's option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (

RT) capability that allows for reset

of the read pointer to its initial position when

RT is pulsed low to allow for

retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.

These FIFOs are fabricated using IDT's high-speed CMOS technology.

They are designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.

FUNCTIONAL BLOCK DIAGRAM

WRITE

CONTROL

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

XIA

WRITE

POINTER

RAM

ARRAY A

512 x 9

1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA

OUTPUTS

RSA

FLA

RTA

XOA

HFA

FFA

EFA

WRITE

CONTROL

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

XIB

WRITE

POINTER

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA

OUTPUTS

RSB

FLB

RTB

3966 drw 01

XOB

HFB

FFB

EFB

(DA

-DA

)

(QA

-QA

)

(QB

-QB

)

(DB

-DB

)

RAM

ARRAY A

512 x 9

1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Commercial

Unit

TERM

Terminal Voltage

0.5 to +7.0

with Respect to GND

STG

Storage Temperature

55 to +125

OUT

DC Output Current

50 to +50

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

3.0

3.3

3.6

GND

Supply Voltage

(1)

Input High Voltage

2.0

+0.5

(2)

Input Low Voltage

0.8

Operating Temperature

Commercial

NOTES:
1. For

RT/RS/XI input, V

= 2.6V (commercial).

2. 1.5V undershoots are allowed for 10ns once per cycle.

RECOMMENDED DC OPERATING

CONDITIONS

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

CAPACITANCE

= +25

C, f = 1.0 MHz)

Symbol

Parameter

(1)

Condition

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

NOTE:
1. Characterized values, not currently tested.

NOTES:
1. Measurements with 0.4

, 0.4

OUT

3. Tested with outputs open (I

OUT

= 0).

4. Tested at f = 20 MHz.
5. All Inputs = V

- 0.2V or GND + 0.2V.

IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85

Commercial

= 15, 20 ns

Symbol

Parameter

Min.

Max.

Unit

(1)

Input Leakage Current (Any Input)

(2)

Output Leakage Current

Output Logic "1" Voltage

2.4

= 2mA

Output Logic "0" Voltage

0.4

= 8mA

CC1

(3,4)

Active Power Supply Current (both FIFOs)

100

CC2

(3,5)

Standby Current (

R=W=RS=FL/RT=V

)

FFA

GND

XOA

HFA

EFA

FFB

GND

XOB

HFB

EFB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

XIA

FLA

RTA

RSA

XIB

FLB

RTB

RSB

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

3966 drw 02

DC ELECTRICAL

CHARACTERISTICS

(1)

(Commercial: V

= 3.3V±0.3V, T

= 0

C to +70

3966 drw 03

30pF*

330

3.3V

OUTPUT

510

or equivalent circuit

Figure 1. Output Load

*Includes scope and jib capacitances.

TSSOP (SO56-2, order code: PA)

TOP VIEW

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

Commercial

IDT72V81L15

IDT72V81L20

IDT72V82L15

IDT72V82L20

IDT72V83L15

IDT72V83L20

IDT72V84L15

IDT72V84L20

IDT72V85L15

IDT72V85L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Shift Frequency

33.3

MHz

Read Cycle Time

Access Time

Read Recovery Time

RPW

Read Pulse Width

(2)

RLZ

Read Pulse Low to Data Bus at Low Z

(3)

WLZ

Write Pulse High to Data Bus at Low Z

(3, 4)

Data Valid from Read Pulse High

RHZ

Read Pulse High to Data Bus at High Z

(3)

Write Cycle Time

WPW

Write Pulse Width

(2)

Write Recovery Time

Data Set-up Time

Data Hold Time

RSC

Reset Cycle Time

Reset Pulse Width

(2)

RSS

Reset Set-up Time

(3)

RSR

Reset Recovery Time

RTC

Retransmit Cycle Time

Retransmit Pulse Width

(2)

RTS

Retransmit Set-up Time

(3)

RTR

Retransmit Recovery Time

EFL

Reset to Empty Flag Low

HFH,FFH

Reset to Half-Full and Full Flag High

RTF

Retransmit Low to Flags Valid

REF

Read Low to Empty Flag Low

RFF

Read High to Full Flag High

RPE

Read Pulse Width after

EF High

WEF

Write High to Empty Flag High

WFF

Write Low to Full Flag Low

WHF

Write Low to Half-Full Flag Low

RHF

Read High to Half-Full Flag High

WPF

Write Pulse Width after

FF High

XOL

Read/Write to

XO Low

XOH

Read/Write to

XO High

XI Pulse Width

(2)

XIR

XI Recovery Time

XIS

XI Set-up Time

NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

= 3.3V±0.3V, T

= 0

C to +70

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

Single Device Mode, this pin acts as the retransmit input. The Single Device
Mode is initiated by grounding the Expansion In (

XI).

The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit

data when the Retransmit Enable control (

RT) input is pulsed low. A retransmit

operation will set the internal read pointer to the first location and will not affect
the write pointer. Read Enable (

R) and Write Enable (W) must be in the high

state during retransmit for the IDT72V81/72V82/72V83/72V84/72V85 respec-
tively. This feature is useful when less than 512/1,024/2,048/4,096/8,192 writes
are performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (

HF), depending on

the relative locations of the read and write pointers.

EXPANSION IN (

XI )

This input is a dual-purpose pin. Expansion In (

XI) is grounded to indicate

an operation in the single device mode. Expansion In (

XI) is connected to

Expansion Out (

XO) of the previous device in the Depth Expansion or Daisy

Chain Mode.

OUTPUTS:

FULL FLAG (

FF )

The Full Flag (

FF) will go low, inhibiting further write operation, when the write

pointer is one location less than the read pointer, indicating that the device is full.
If the read pointer is not moved after Reset (

RS), the Full-Flag (FF) will go low

after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.

EMPTY FLAG (

EF )

The Empty Flag (

EF) will go low, inhibiting further read operations, when

the read pointer is equal to the write pointer, indicating that the device is
empty.

EXPANSION OUT/HALF-FULL FLAG (

XO/HF

HF )

This is a dual-purpose output. In the single device mode, when Expan-

sion In (

XI) is grounded, this output acts as an indication of a half-full memory.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (

HF) will be set low and will remain set until the

difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (

HF) is then reset

by using rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (

XI) is connected to Expansion

Out (

XO) of the previous device in the Daisy Chain by providing a pulse to the

next device when the previous device reaches the last location of memory.

DATA OUTPUTS ( Q

 Q

)

Data outputs for 9-bit wide data. This data is in a high impedance

condition whenever Read (

R) is in a high state.

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D

 D

)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

RS )

Reset is accomplished whenever the Reset (

RS) input is taken to a low state.

During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place. Both
the Read Enable (

R ) and Write Enable ( W

W ) inputs must be in the high

state during the window shown in Figure 2, (i.e., t

RSS

before the rising

edge of

RS ) and should not change until t

RSR

after the rising edge of

RS. Half-Full Flag ( HF

HF ) will be reset to high after Reset ( RS

RS ).

WRITE ENABLE (

W )

A write cycle is initiated on the falling edge of this input if the Full Flag (

FF)

is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (

W). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (

HF) will be set to low and will remain set until the

difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (

HF) is then reset

by the rising edge of the read operation.

To prevent data overflow, the Full Flag (

FF) will go low, inhibiting further write

operations. Upon the completion of a valid read operation, the Full Flag (

FF)

will go high after t

RFF

, allowing a valid write to begin. When the FIFO is full, the

internal write pointer is blocked from

W, so external changes in W will not affect

the FIFO when it is full.

READ ENABLE (

R )

A read cycle is initiated on the falling edge of the Read Enable (

R) provided

the Empty Flag (

EF) is not set. The data is accessed on a First-In/First-Out basis,

independent of any ongoing write operations. After Read Enable (

R) goes high,

the Data Outputs (Q

) will return to a high impedance condition until the

next Read operation. When all data has been read from the FIFO, the Empty
Flag (

EF) will go low, allowing the "final" read cycle but inhibiting further read

operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (

EF) will go high

after t

WEF

and a valid Read can then begin. When the FIFO is empty, the internal

read pointer is blocked from

R so external changes in R will not affect the FIFO

when it is empty.

FIRST LOAD/RETRANSMIT (

FL/RT

RT )

This is a dual-purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first loaded (see Operating Modes). In the

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

Figure 9. Half-Full Flag Timing

Figure 10. Expansion Out

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is monitored by each

system (i.e.

FF is monitored on the device where W is used; EF is monitored on

the device where

R is used).

Single Device Mode

A single IDT72V81/72V82/72V83/72V84/72V85 may be used when the

application requirements are for 512/1,024/2,048/4,096/8,192 words or less.
These FIFOs are in a Single Device Configuration when the Expansion In (

XI)

control input is grounded (see Figure 12).

Depth Expansion

These devices can easily be adapted to applications when the requirements

are for greater than 512/1,024/2,048/4,096/8,192 words. Figure 14 demon-

strates a four-FIFO Depth Expansion using two IDT72V81/72V82/72V83/
72V84/72V85s. Any depth can be attained by adding additional IDT72V81/
72V82/72V83/72V84/72V85s. These FIFOs operate in the Depth Expansion
mode when the following conditions are met:

1. The first FIFO must be designated by grounding the First Load (

FL) control

input.

2. All other FIFOs must have

FL in the high state.

3. The Expansion Out (

XO) pin of each device must be tied to the Expansion

In (

XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag (

FF) and Empty

Flag (

EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all

must be set to generate the correct composite

FF or EF). See Figure 14.

5. The Retransmit (

RT) function and Half-Full Flag (HF) are not available in

the Depth Expansion Mode.

WRITE TO

FIRST PHYSICAL

LOCATION

READ FROM

FIRST PHYSICAL

LOCATION

XIS

XIR

XIS

3966 drw 13

3966 drw 12

WRITE TO

LAST PHYSICAL

LOCATION

XOL

XOH

READ FROM

LAST PHYSICAL

LOCATION

XOL

XOH

RHF

3966 drw 11

HALF-FULL OR LESS

MORE THAN HALF-FULL

HALF-FULL OR LESS

WHF

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the corresponding

input control signals of multiple FIFOs. Status flags (

EF, FF and HF) can be

detected from any one FIFO. Figure 13 demonstrates an 18-bit word width by
using the two FIFOs contained in the IDT72V81/72V82/72V83/72V84/72V85s.
Any word width can be attained by adding FIFOs (Figure 13).

Bidirectional Operation

Applications which require data buffering between two systems (each

system capable of Read and Write operations) can be achieved by pairing
IDT72V81/72V82/72V83/72V84/72V85s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read flow-through

and write flow-through mode. For the read flow-through mode (Figure 17), the

FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (t

WEF

+ t

) ns after the rising

edge of

W, called the first write edge, and it remains on the bus until the R line

is raised from low-to-high, after which the bus would go into a three-state mode
after t

RHZ

ns. The

EF line would have a pulse showing temporary deassertion

and then would be asserted.

In the write flow-through mode (Figure 18), the FIFO permits the writing

of a single word of data immediately after reading one word of data from a
full FIFO. The

R line causes the FF to be deasserted but the W line being low

causes it to be asserted again in anticipation of a new data word. On the rising
edge of

W, the new word is loaded in the FIFO. The W line must be toggled when

FF is not asserted to write new data in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be applied together

in a straightforward manner to achieve large FIFO arrays (see Figure 15).

Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode

Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode

XIA

XIB

HFB

HFA

WRITE (

)

FULL FLAG (

FFA

)

RESET (

)

READ (

)

EMPTY FLAG (

EFB

)

RETRANSMIT (

)

DATA

OUT

(Q)

3966 drw 15

FIFO A

FIFO B

72V81/72V82/72V83
72V84/72V85

DATA

(D)

WRITE (

)

DATA IN (D)

FULL FLAG (

)

RESET (

)

READ (

)

DATA OUT (Q)

EMPTY FLAG (

)

RETRANSMIT (

)

EXPANSION IN (

)

(

)

IDT

72V81
72V82
72V83
72V84
72V85

(HALF-FULL FLAG)

3966 drw 14

FIFO

A or B

Commercial Temperature Range

IDT72V81/72V82/72V83/72V84/72V85

TABLE IIRESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset First Device

(1)

Location Zero

Reset All Other Devices

(1)

Location Zero

Read/Write

(1)

NOTE:
1.

XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

XI = Expan-

sion Input,

HF = Half-Full Flag Output

TABLE IRESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset

Location Zero

Retransmit

Location Zero

Unchanged

Read/Write

Increment

(1)

Increment

(1)

NOTE:
1. Pointer will increment if flag is High.

Figure 14. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 and 32,768 x 9 FIFO Memory (Depth Expansion)

FFB

EFB

FLB

XOB

RSA

FULL

EMPTY

XIB

FFA

EFA

FLA

XOA

XIA

FFB

EFB

FLB

XIB

3966 drw 16

XOA

FIFO A

FIFO B

FIFO A

FIFO B

XIA

XOB

EFA

FLA

FFA

72V81/72V82
72V83/72V84
72V85

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The Async FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-6116

408-330-1753

Santa Clara, CA 95054

fax: 408-492-8674

email: FIFOhelp@idt.com

www.idt.com*

PFPkg: www.idt.com/docs/PSC4039.pdf

IDT

XXXX

Device Type

XXX

Speed

Power

Package

Process/

Temperature

Range

Blank

72V81
72V82
72V83
72V84
72V85

15
20

Commercial (0

C to +70

512 x 9

3.3V Dual FIFO

1,024 x 9

3.3V Dual FIFO

2,048 x 9

3.3V Dual FIFO

4,096 x 9

3.3V Dual FIFO

8,192 x 9

3.3V Dual FIFO

Low Power

Thin Shrink SOIC (TSSOP, S056-2)

Access Time (t

) Speed

in Nanoseconds

3966 drw 21

Commercial

Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

NOTE:
1. Industrial temperature range is available by special order.

DATA

OUT

WFF

RFF

WPF

DATA

VALID

DATA

OUT

VALID

3966 drw 20

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V83

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V83