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Электронный компонент: 72V845

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2001 Integrated Device Technology, Inc.
DSC-4295/1
APRIL 2001
3.3 VOLT CMOS DUAL SyncFIFOTM
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
OUTPUT
REGISTER
OFFSET
REGISTER
FLAG
LOGIC
FFA
/
IRA
PAFA
EFA
/
ORA
PAEA
HFA
/(
WXOA
)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENA
DA
0
-DA
17
LDA
RSA
(
HFA
)/
WXOA
WXIA
RENA
RCLKA
OEA
QA
0
-QA
17
RXOA
RXIA
FLA
WCLKA
INPUT
REGISTER
OUTPUT
REGISTER
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
OFFSET
REGISTER
FLAG
LOGIC
FFB
/
IRB
PAFB
EFB
/
ORB
PAEB
HFB
/(
WXOB
)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENB
DB0-DB17
LDB
RSB
(
HFB
)/
WXOB
WXIB
RENB
RCLKB
OEB
QB
0
-QB
17
RXOB
RXIB
FLB
WCLKB
4295 drw 01
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
FEATURES:




The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs




The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs




The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs




The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs




The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs




Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint




Ideal for the following applications:
Network switching
Two level prioritization of parallel data
Bidirectional data transfer
Bus-matching between 18-bit and 36-bit data paths
Width expansion to 36-bit per package
Depth expansion to 8,192 words per package




10 ns read/write cycle time




5V input tolerant




IDT Standard or First Word Fall Through timing




Single or double register-buffered Empty and Full Flags




Easily expandable in depth and width




Asynchronous or coincident Read and Write Clocks




Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings




Half-Full flag capability




Output enable puts output data bus in high-impedance state




High-performance submicron CMOS technology




Available in a 128-pin thin quad flatpack (TQFP)




Industrial temperature range (40C to +85C) is available
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked) First-in, First-out (FIFO) memories designed to run
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845 device is functionally equiva-
lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
package with all associated control, data, and flag lines assigned to
independent pins. These devices are very high-speed, low-power First-In,
First-Out (FIFO) memories with clocked read and write controls. These
2
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATIONS
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
FIFOs are applicable for a wide variety of data buffering needs, such as
optical disk controllers, Local Area Networks (LANs), and interprocessor
communication.
Each of the two FIFOs contained in these devices has an 18-bit input
and output port. Each input port is controlled by a free-running clock
(WCLK), and an input enable pin (
WEN). Data is read into the synchronous
FIFO on every clock when
WEN is asserted. The output port of each FIFO
bank is controlled by another clock pin (RCLK) and another enable pin
(
REN). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (
OE) is provided on the read port
of each FIFO for three-state control of the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(
EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (
PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated
by asserting the Load pin (
LD). A Half-Full flag (HF) is available for each
FIFO that is implemented as a single device.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating
REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through (FWFT) mode. The
XI and XO pins are used to
expand the FIFOs. In depth expansion configuration,
FL is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
IDT's high-speed submicron CMOS technology.
V
CC
LDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PAFA
RXIA
FFA
WXOA
/
HFA
RXOA
QA0
QA1
GND
QA2
QA3
V
CC
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PAEB
FLB
WCLKB
WENB
WXIB
V
CC
PAFB
RXIB
FFB
WXOB
/
HFB
RXOB
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
OEA
RSA
V
CC
GND
EFA
QA17
QA16
GND
QA15
V
CC
QA14
QA13
GND
QA12
QA11
V
CC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
RCLKB
RENB
LDB
OEB
RSB
V
CC
GND
EFB
WXIA
WENA
WCLKA
FLA
PAEA
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA16
DA17
GND
RCLKA
RENA
QB0
QB1
GND
Q
B
2
QB3
V
CC
QB4
GND
QB5
QB6
QB7
QB8
GND
QB9
QB10
V
CC
QB11
QB12
GND
QB13
QB14
V
CC
QB15
GND
QB16
QB17
104
103
INDEX
GND
DA15
4295 drw 02
DESCRIPTION (CONTINUED)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
PIN DESCRIPTION
Symbol
Name
I/O
Description
DA
0
DA
17
Data Inputs
I
Data inputs for an 18-bit bus.
DB
0
-DB
17
RSA
Reset
I
When
RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and
RSB
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLKA
Write Clock
I
When
WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WCLKB
WENA
Write Enable
I
When
WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
WENB
When
WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
RCLKA
Read Clock
I
When
REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not
RCLKB
empty.
RENA
Read Enable
I
When
REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN
RENB
is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the
EF is low.
OEA
Output Enable
I
When
OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
OEB
high-impedance state.
LDA
Load
I
When
LD is LOW, data on the inputs D0D11 is written to the offset and depth registers on the LOW-to-HIGH
LDB
transition of the WCLK, when
WEN is LOW. When LD is LOW, data on the outputs Q0Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN is LOW.
FLA
First Load
I
In the single device or width expansion configuration,
FL together with WXI and RXI etermine if the mode is IDT
FLB
Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE/PAF flags are synchronous
or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration,
FL is grounded on the first
device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXIA
Write Expansion
I
In the single device or width expansion configuration,
WXI together with FL and RXI Input determine if the mode
WXIB
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI is connected to WXO (Write Expansion
Out) of the previous device.
RXIA
Read Expansion
I
In the single device or width expansion configuration,
RXI together with FL and WXI, Input determine if the mode
RXIB
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI is connected to RXO (Read
Expansion Out) of the previous device.
FFA/IRA
Full Flag/
O
In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory is full.
FFB/IRB
Input Ready
In the FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EFA/ORA
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory is
EFB/ORB
Output Ready
empty. In FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data available at
the outputs.
PAEA
Programmable
O
When
PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset
PAEB
Almost-Empty flag
at reset is 31 from empty for IDT72V805LB, 63 from empty for IDT72V815LB, and 127 from empty for IDT7V2825LB/
72V835LB/72V845LB.
PAFA
Programmable
O
When
PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
PAFB
Almost-Full Flag
at reset is 31 from full for IDT72V805LB, 63 from full for IDT72V815LB, and 127 from full for IDT72V825LB/
72V835LB/72V845LB.
WXOA/HFA
Write Expansion
O
In the single device or width expansion configuration, the device is more than half full Out/Half-Full Flag
WXOB/
HFB
when
HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device
when the last location in the FIFO is written.
RXOA
Read Expansion
O
In the depth expansion configuration, a pulse is sent from
RXO to RXI of the next device when the last location
RXOB
Out
in the FIFO is read.
QA
0
QA
17
Data Outputs
O
Data outputs for an 18-bit bus.
QB
0
-QB
17
V
CC
Power
+3.3V power supply pins.
GND
Ground
Ground pins.
4
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2)
Input
V
IN
= 0V
10
pF
Capacitance
C
OUT
(1,2)
Output
V
OUT
= 0V
10
pF
Capacitance
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
Commercial/Industrial
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
2.0
--
5.0
V
Commercial/Industrial
V
IL
(1)
Input Low Voltage
--
--
0.8
V
Commercial/Industrial
T
A
Operating Temperature
0
--
70
C
Commercial
T
A
Operating Temperature
-40
85
C
Industrial
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol
Rating
Commercial
Unit
V
TERM
Terminal Voltage
0.5 to +5
V
with respect to GND
T
STG
Storage
55 to +125
C
Temperature
I
OUT
DC Output Current
50 to +50
mA
CAPACITANCE
(T
A
= +25C, f = 1.0MHz)
NOTES:
1. With output deselected, (
OE
V
IH
).
2. Characterized values, not currently tested.
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
Commercial & Industrial
(1)
t
CLK
= 10, 15, 20 ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
LI
(2)
Input Leakage Current (any input)
1
--
1
A
I
LO
(3)
Output Leakage Current
10
--
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8 mA
--
--
0.4
V
I
CC1
(4,5,6)
Active Power Supply Current
--
--
60
mA
I
CC2
(4,7)
Standby Current
--
--
10
mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V 0.3V, T
A
= 0C to +70C; Industrial: V
CC
= 3.3V
0.3V, TA = -40
C to +85
C)
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4
V
IN
V
CC
.
3.
OE
V
IH
, 0.4
V
OUT
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical I
CC1
= 2[2.04 + 0.88*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING DC
CONDITIONS
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
5
Commercial
Com'l & Ind'l
(2)
Commercial
IDT72V805L10
IDT72V805L15
IDT72V805L20
IDT72V815L10
IDT72V815L15
IDT72V815L20
IDT72V825L10
IDT72V825L15
IDT72V825L20
IDT72V835L10
IDT72V835L15
IDT72V835L20
IDT72V845L10
IDT72V845L15
IDT72V845L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
S
Clock Cycle Frequency--
100
--
66.7
--
50
MHz
t
A
Data Access Time
2
6.5
2
10
2
12
ns
t
CLK
Clock Cycle Time
10
--
15
--
20
--
ns
t
CLKH
Clock HIGH Time
4.5
--
6
--
8
--
ns
t
CLKL
Clock LOW Time
4.5
--
6
--
8
--
ns
t
DS
Data Setup Time
3
--
4
--
5
--
ns
t
DH
Data Hold Time
0.5
--
1
--
1
--
ns
t
ENS
Enable Setup Time
3
--
4
--
5
--
ns
t
ENH
Enable Hold Time
0.5
--
1
--
1
--
ns
t
RS
Reset Pulse Width
(1)
10
--
15
--
20
--
ns
t
RSS
Reset Setup Time
8
--
10
--
12
--
ns
t
RSR
Reset Recovery Time
8
--
10
--
12
--
ns
t
RSF
Reset to Flag and Output Time
--
15
--
15
--
20
ns
t
OLZ
Output Enable to Output in Low-Z
(3)
0
--
0
--
0
--
ns
t
OE
Output Enable to Output Valid
--
6
3
8
3
10
ns
t
OHZ
Output Enable to Output in High-Z
(3)
1
6
3
8
3
10
ns
t
WFF
Write Clock to Full Flag
--
6.5
--
10
--
12
ns
t
REF
Read Clock to Empty Flag
--
6.5
--
10
--
12
ns
t
PAFA
Clock to Asynchronous Programmable
--
17
--
20
--
22
ns
Almost-Full Flag
t
PAFS
Write Clock to Synchronous
--
8
--
10
--
12
ns
Programmable Almost-Full Flag
t
PAEA
Clock to Asynchronous Programmable
--
17
--
20
--
22
ns
Almost-Empty Flag
t
PAES
Read Clock to Synchronous
--
8
--
10
--
12
ns
Programmable Almost-Empty Flag
t
HF
Clock to Half-Full Flag
--
17
--
20
--
22
ns
t
XO
Clock to Expansion Out
--
6.5
--
10
--
12
ns
t
XI
Expansion In Pulse Width
3
--
6.5
--
8
--
ns
t
XIS
Expansion In Setup Time
3
--
5
--
8
--
ns
t
SKEW1
Skew time between Read Clock &
5
--
6
--
8
--
ns
Write Clock for
FF/IR and EF/OR
t
SKEW2
(4)
Skew time between Read Clock &
14
--
18
--
20
--
ns
Write Clock for
PAE and PAF
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V 0.3V, T
A
= 0C to +70C; Industrial: V
CC
= 3.3V
0.3V, TA = -40
C to +85
C)
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Values guaranteed by design, not currently tested.
4. t
SKEW2
applies to synchronous
PAE and synchronous PAF only.
30pF*
330
3.3V
510
D.U.T.
4295 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
6
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TIMING MODES:
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
The IDT72V805/72V815/72V825/72V835/72V845 support two different
timing modes of operation. The selection of which mode will operate is
determined during configuration at Reset (
RS). During a RS operation, the
First Load (
FL), Read Expansion Input ( RXI), and Write Expansion Input
(
WXI) pins are used to select the timing mode per the truth table shown in
Table 3. In IDT Standard Mode, the first word written to an empty FIFO will
not appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating Read Enable
(
REN) and enabling a rising Read Clock (RCLK) edge, will shift the word
from internal memory to the data output lines. In FWFT mode, the first word
written to an empty FIFO is clocked directly to the data output lines after
three transitions of the RCLK signal. A
REN does not have to be asserted
for accessing the first word.
Various signals, both input and output signals operate differently depend-
ing on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(
WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (
EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (
PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the Empty Offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (
HF) would toggle to LOW
once the 129th (72V805), 257th (72V815), 513th (72V825), 1,025th
(72V835), and 2,049th (72V845) word respectively was written into the
FIFO. Continuing to write data into the FIFO will cause the Programmable
Almost-Full flag (
PAF) to go LOW. Again, if no reads are performed, the
PAF will go LOW after (256-m) writes for the IDT72V805, (512-m) writes for
the IDT72V815, (1,024-m) writes for the IDT72V825, (2,048m) writes for
the IDT72V835 and (4,096m) writes for the IDT72V845. The offset "m" is
the Full Offset value. This parameter is also user programmable. See
section on Programmable Flag Offset Loading. If there is no Full Offset
specified, the
PAF will be LOW when the device is 31 away from completely
full for IDT72V805, 63 away from completely full for IDT72V815, and 127
away from completely full for the IDT72V825/72V835/72V845.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset,
FF will go LOW
after D writes to the FIFO. D = 256 writes for the IDT72V805, 512 for the
IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096
for the IDT72V845, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and the Half-Full flag (HF) to
go HIGH at the conditions described in Table 1. If further read operations
occur, without write operations, the Programmable Almost-Empty flag
(
PAE) will go LOW when there are n words in the FIFO, where n is the Empty
Offset value. If there is no Empty Offset specified, the
PAE will be LOW when
the device is 31 away from completely empty for IDT72V805, 63 away from
completely empty for IDT72V815, and 127 away from completely empty for
IDT72V825/72V835/72V845. Continuing read operations will cause the
FIFO to be empty. When the last word has been read from the FIFO, the
EF
will go LOW inhibiting further read operations.
REN is ignored when the
FIFO is empty.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO,
WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (
OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO.
PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the Empty Offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HF would toggle to LOW once the 130th
(72V805), 258th (72V815), 514th (72V825), 1,026th (72V835), and 2,050th
(72V845) word respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the
PAF to go LOW. Again, if no reads are
performed, the
PAF will go LOW after (257-m) writes for the IDT72V805,
(513-m) writes for the IDT72V815, (1,025-m) writes for the IDT72V825,
(2,049m) writes for the IDT72V835 and (4,097m) writes for the IDT72V845,
where m is the Full Offset value. The default setting for this value is stated
in the footnote of Table 2.
When the FIFO is full, the Input Ready (
IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset,
IR will go
HIGH after D writes to the FIFO. D = 257 writes for the IDT72V805, 513 for
the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and
4,097 for the IDT72V845. Note that the additional word in FWFT mode is
due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the
PAE will go LOW when there are n + 1 words in the
FIFO, where n is the Empty Offset value. If there is no Empty Offset
specified, the
PAE will be LOW when the device is 32 away from completely
empty for IDT72V805, 64 away from completely empty for IDT72V815, and
128 away from completely empty for IDT72V825/72V835/72V845. Continu-
ing read operations will cause the FIFO to be empty. When the last word has
been read from the FIFO,
OR will go HIGH inhibiting further read operations.
REN is ignored when the FIFO is empty.
PROGRAMMABLE FLAG LOADING
Full and Empty flag Offset values can be user programmable. The
IDT72V805/72V815/72V825/72V835/72V845 has internal registers for these
offsets. Default settings are stated in the footnotes of Table 1 and Table 2.
Offset values are loaded into the FIFO using the data input lines D0-D11.
To load the offset registers, the Load (
LD) pin and WEN pin must be held
LOW. Data present on D0-D11 will be transferred in to the Empty Offset
register on the first LOW-to-HIGH transition of WCLK. By continuing to hold
the
LD and WEN pin low, data present on D0-D11 will be transferred into
the Full Offset register on the next transition of the WCLK. The third
transition again writes to the Empty Offset register. Writing all offset
registers does not have to occur at one time. One or two offset registers can
be written and then by bringing the
LD pin HIGH, the FIFO is returned to
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
7
Number of Words in FIFO
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
IR PAF HF PAE OR
0
0
0
0
0
L
H
H
L
H
1 to (n + 1)
(1)
1 to (n + 1)
(1)
1 to (n + 1)
(1)
1 to (n + 1)
(1)
1 to (n + 1)
(1)
L
H
H
L
L
(n + 2) to 129
(n + 2) to 257
(n + 2) to 513
(n + 2) to 1,025
(n + 2) to 2,049
L
H
H
H
L
130 to (257-(m+1))
(2)
258 to (513-(m+1))
(2)
514 to (1,025-(m+1))
(2)
1,026 to (2,049-(m+1))
(2)
2,050 to (4,097-(m+1))
(2)
L
H
L
H
L
(257-m) to 256
(513-m) to 512
(1,025-m) to 1,024
(2,049-m) to 2,048
(4,097-m) to 4,096
L
L
L
H
L
257
513
1,025
2,049
4,097
H
L
L
H
L
normal read/write operation. When the
LD pin and WEN are again set LOW,
the next offset register in sequence is written.
The contents of the offset registers can be read on the data output lines
Q0-Q11 when the
LD pin is set LOW and REN is set LOW. Data can then
be read on the next LOW-to-HIGH transition of RCLK. The first transition
of RCLK will present the Empty Offset value to the data output lines. The
next transition of RCLK will present the Full Offset value. Offset register
content can be read out in the IDT Standard mode only. It cannot be read
in the FWFT mode.
SYNCHRONOUS VS ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
during the "Configuration at Reset" cycle described in Table 3 with either
asynchronous or synchronous timing for
PAE and PAF flags.
If asynchronous
PAE/PAF configuration is selected (as per Table 3), the
PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the
PAF is
asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-
grams, see Figure 13 for asynchronous
PAE timing and Figure 14 for
asynchronous
PAF timing.
If synchronous
PAE/PAF configuration is selected , the PAE is asserted
and updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. For
detail timing diagrams, see Figure 22 for synchronous
PAE timing and
Figure 23 for synchronous
PAF timing.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
during the "Configuration at Reset" cycle described in Table 4 with single,
double or triple register-buffered flag output signals. The various combina-
tions available are described in Table 4 and Table 5. In general, going from
single to double or triple buffered flag outputs removes the possibility of
metastable flag indications on boundary states (i.e, empty or full condi-
tions). The trade-off is the addition of clock cycle delays for the respective
flag to be asserted. Not all combinations of register-buffered flag outputs
are supported. Register-buffered outputs apply to the Empty Flag and Full
Flag only. Partial flags are not effected. Table 4 and Table 5 summarize
the options available.
TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
FF PAF
HF PAE EF
0
0
0
0
0
H
H
H
L
L
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
H
H
H
L
H
(n + 1) to 128
(n + 1) to 256
(n + 1) to 512
(n + 1) to 1,024
(n + 1) to 2,048
H
H
H
H
H
129 to (256-(m+1))
(2)
257 to (512-(m+1))
(2)
513 to (1,024-(m+1))
(2)
1,025 to (2,048-(m+1))
(2)
2,049 to (4,096-(m+1))
(2)
H
H
L
H
H
(256-m) to 255
(512-m)
to 511
(1,024-m) to 1,023
(2,048-m) to 2,047
(4,096-m) to 4,095
H
L
L
H
H
256
512
1,024
2,048
4,096
L
L
L
H
H
TABLE 2 STATUS FLAGS FOR FWFT MODE
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n=31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m=31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n = 31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m = 31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
8
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Output Ready (
OR)
Input Ready (
IR)
Partial Flags
Programming at Reset
Flag Timing
FL
RXI
WXI
Diagrams
Triple
Double
Asynch
0
0
1
Figure 27
Triple
Double
Sync
1
0
1
Figure 20, 21
Empty Flag (
EF)
Full Flag (
FF)
Partial Flags
Programming at Reset
Flag Timing
Buffered Output
Buffered Output
Timing Mode
FL
RXI
WXI
Diagrams
Single
Single
Asynch
0
0
0
Figure 9, 10
Single
Single
Sync
1
0
0
Figure 9, 10
Double
Double
Asynch
0
1
0
Figure 24, 26
Double
Double
Synch
1
1
0
Figure 24, 26
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO TIMING MODE
0
0
0
Single Register-Buffered
Single Register-Buffered
Asynchronous
Standard
Empty Flag
Full Flag
0
0
1
Triple Register-Buffered
Double Register-Buffered
Asynchronous
FWFT
Output Ready Flag
Input Ready Flag
0
1
0
Double Register-Buffered
Double Register-Buffered
Asynchronous
Standard
Empty Flag
Full Flag
0
(1)
1
1
Single Register-Buffered
Single Register-Buffered
Asynchronous
Standard
Empty Flag
Full Flag
1
0
0
Single Register-Buffered
Single Register-Buffered
Synchronous
Standard
Empty Flag
Full Flag
1
0
1
Triple Register-Buffered
Double Register-Buffered
Synchronous
FWFT
Output Ready Flag
Input Ready Flag
1
1
0
Double Register-Buffered
Double Register-Buffered
Synchronous
Standard
Empty Flag
Full Flag
1
(2)
1
1
Single Register-Buffered
Single Register-Buffered
Asynchronous
Standard
Empty Flag
Full Flag
NOTES:
1. In a daisy-chain depth expansion,
FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion,
FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO
and
WXO outputs of the preceding device.
TABLE 3 TRUTH TABLE FOR CONFIGURATION AT RESET
TABLE 4 REGISTER-BUFFERED FLAG OUTPUT OPTIONS IDT STANDARD MODE
TABLE 5 REGISTER-BUFFERED FLAG OUTPUT OPTIONS FWFT MODE
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
9
NOTE:
1. The same selection sequence applies to reading from the registers.
REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
EMPTY OFFSET REGISTER
17
11
0
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
FULL OFFSET REGISTER
17
11
0
DEFAULT VALUE
DEFAULT VALUE
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
4295 drw 04
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (
RSA/RSB)
Reset is accomplished whenever the Reset (
RSA/RSB) input is taken to
a LOW state. During reset, both internal read and write pointers are set to
the first location. A reset is required after power-up before a write operation
can take place. The Half-Full flag (
HFA/HFB) and Programmable Almost-
Full flag (
PAFA/PAFB) will be reset to HIGH after t
RSF
. The Programmable
Almost-Empty flag (
PAEA/PAEB) will be reset to LOW after t
RSF
. The Full
Flag (
FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset
to LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During
reset, the output register is initialized to all zeros and the offset registers
are initialized to their default values.
WRITE CLOCK (WCLKA/WCLKB)
A write cycle is initiated on the LOW-to-HIGH transition of the Write
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (
WENA/WENB)
When the
WENA/WENB input is LOW, data may be loaded into the
FIFO RAM array on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
When
WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard Mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle,
FF will go HIGH allowing a write to occur. The FF flag is updated on
the rising edge of WCLK.
To prevent data overflow in the FWFT mode, Input Ready (
IRA,IRB) will
go HIGH, inhibiting further write operations. Upon the completion of a valid
read cycle,
IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
READ CLOCK (RCLKA/RCLKB)
Data can be read on the outputs on the LOW-to-HIGH transition of the
Read Clock (RCLKA/RCLKB), when Output Enable (
OEA/OEB) is set
LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (
RENA/RENB)
When Read Enable (
RENA/RENB) is LOW, data is loaded from the RAM
array into the output register on the rising edge of every RCLK cycle if the
device is not empty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-
Qn maintain the previous data value.
Figure 2. Writing to Offset Registers
Figure 3. Offset Register Location and Default Values
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using
REN. When the
last word has been read from the FIFO, the Empty Flag (
EFA/EFB) will go
LOW, inhibiting further read operations.
REN is ignored when the FIFO is
empty. Once a write is performed,
EF will go HIGH allowing a read to occur.
The
EF flag is updated on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ t
SKEW
after the first write.
REN does not need to be asserted LOW. In
order to access all other words, a read must be executed using
REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (
ORA/ORB) will go HIGH with a true read (RCLK with
REN = LOW), inhibiting further read operations. REN is ignored when the
FIFO is empty.
LD
WEN
WCLK
Selection
0
0
Writing to offset registers:
Empty Offset
Full Offset
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
10
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (
OEA/OEB)
When Output Enable (
OEA/OEB) is enabled (LOW), the parallel output
buffers receive data from the output register. When
OE is disabled (HIGH),
the Q output data bus is in a high-impedance state.
LOAD (
LDA/LDB)
The IDT72V805/72V815/72V825/72V835/72V845 devices contain two
12-bit offset registers with data on the inputs, or read on the outputs. When
the Load (
LDA/LDB) pin is set LOW and WEN is set LOW, data on the
inputs D0-D11 is written into the Empty offset register on the first LOW-to-
HIGH transition of the Write Clock (WCLK). When the
LD pin and WEN are
held LOW then data is written into the Full offset register on the second
LOW-to-HIGH transition of WCLK. The third transition of WCLK again
writes to the Empty offset register.
However, writing all offset registers does not have to occur at one time.
One or two offset registers can be written and then by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When the LD
pin is set LOW, and WEN is LOW, the next offset register in sequence is
written.
When the
LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when
the
LD pin is set LOW and REN is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read Clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The
read and write pointers operate independently). Offset register content
can be read out in the IDT Standard mode only. It is inhibited in the FWFT
mode.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (
FLA/FLB)
For the single device mode, see Table I for additional information. In
the Daisy Chain Depth Expansion configuration,
FLA/FLB is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
WRITE EXPANSION INPUT (
WXIA/WXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information.
WXIA/WXIB is connected to Write Expansion Out
(
WXOA/WXOB) of the previous device in the Daisy Chain Depth Expan-
sion mode.
READ EXPANSION INPUT (
RXIA/RXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information.
RXIA/RXIB is connected to Read Expansion Out
(
RXOA/RXOB) of the previous device in the Daisy Chain Depth Expansion
mode.
OUTPUTS:
FULL FLAG/INPUT READY (
FFA/IRA, FFB/IRB)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FFA/
FFB) function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When
FF is HIGH, the FIFO is not full. If no reads
are performed after a reset,
FF will go LOW after D writes to the FIFO.
D = 256 writes for the IDT72V805, 512 for the IDT72V815, 1,024 for the
IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845.
In FWFT mode, the Input Ready (
IRA/IRB) function is selected. IR goes
LOW when memory space is available for writing in data. When there is
no longer any free space left,
IR goes HIGH, inhibiting further write
operations.
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72V205LB, 513 for the IDT72V215LB, 1,025 for the IDT72V225LB,
2,049 for the IDT72V235LB and 4,097 for the IDT72V245LB. Note that the
additional word in FWFT mode is due to the capacity of the memory plus
output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (
EFA/ORA, EFB/ORB)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(
EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When
EF is HIGH, the FIFO is not
empty.
In FWFT mode, the Output Ready (
ORA/ORB) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs.
OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs.
OR
goes HIGH only with a true read (RCLK with
REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until
OR goes LOW again.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (
PAFA/PAFB)
The Programmable Almost-Full flag (
PAFA/PAFB) will go LOW when
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (
RS), the PAF will go LOW after (256-m) writes
for the IDT72V805, (512-m) writes for the IDT72V815, (1,024-m) writes for
the IDT72V825, (2,048m) writes for the IDT72V835 and (4,096-m) writes
for the IDT72V845. The offset "m" is defined in the FULL offset register.
In FWFT mode, if no reads are performed,
PAF will go LOW after (257-
m) writes for the IDT72V805, (513-m) writes for the IDT72V815, (1,025-m)
writes for the IDT72V825, (2,049-m) writes for the IDT72V835 and (4,097-
m) writes for the IDT72V845. The default values for m are noted in Table
1 and 2.
If asynchronous
PAF configuration is selected, the PAF is asserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK).
If synchronous
PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAEA/PAEB)
The
PAE flag will go LOW when the FIFO reads the almost-empty
condition. In IDT Standard mode,
PAE will go LOW when there are n words
or less in the FIFO. In FWFT mode, the
PAE will go LOW when there are
n+1 words or less in the FIFO. The offset "n" is defined as the Empty offset.
The default values for n are noted in Table 1 and 2.
If asynchronous
PAE configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous
PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
11
WRITE EXPANSION OUT/HALF-FULL FLAG
(
WXOA/HFA, WXOB/HFB)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (
WXIA/WXIB) and/or Read Expansion In
(
RXIA/RXIB) are grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled, and at the LOW-to-HIGH transition of
the next write cycle, the Half-Full flag goes LOW and will remain set until
the difference between the write pointer and read pointer is less than or
equal to one half of the total memory of the device. The Half-Full flag (
HFA/
HFB) is then reset to HIGH by the LOW-to-HIGH transition of the Read
Clock (RCLK). The
HF is asynchronous.
In the Daisy Chain Depth Expansion mode,
WXI is connected to WXO
of the previous device. This output acts as a signal to the next device in
the Daisy Chain by providing a pulse when the previous device writes to
the last location of memory.
READ EXPANSION OUT (
RXOA/RXOB)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(
RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the
previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device reads from the last
location of memory.
DATA OUTPUTS (Q
0
-Q
17
, QB
0
-QB
17
)
Q
0
-Q
17
are data outputs for 18-bit wide data.
12
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
WCLK
D
0
- D
17
WEN
FF
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
DH
t
ENH
t
WFF
t
WFF
DATA IN VALID
NO OPERATION
RCLK
SKEW1
t
(1)
REN
4295 drw 06
NOTES:
1. Single device mode (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to V
CC
or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if
OE = 0 and tri-state if OE = 1.
RS
REN
,
WEN
,
LD
PAE
PAF
,
WXO
/
HF
,
RXO
t
RSR
Q
0
- Q
17
OE
= 0
OE
= 1
(1)
4295 drw 05
t
RSS
CONFIGURATION SETTING
t
RSR
FL
,
RXI
,
WXI
RCLK, WCLK
FF
/
IR
RSF
t
EF
/
OR
FWFT Mode
IDT Standard Mode
(3)
(2)
RSF
t
RSF
t
RSF
t
RSF
t
t
RS
Figure 5. Reset Timing
(2)
Figure 6. Write Cycle Timing with Single Register-Buffered
FF
(IDT Standard Mode)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
13
NO OPERATION
RCLK
REN
EF
t
ENS
t
ENH
VALID DATA
t
OLZ
Q
0
- Q
17
OE
WCLK
WEN
4295 drw 07
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
SKEW1
t
(1)
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH during the current clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then
EF may not change state until the next RCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
WCLK
D
0
- D
17
WEN
RCLK
EF
Q
0
- Q
17
REN
t
DS
t
ENS
t
REF
0
1
2
3
D
D
D
D
0
1
D
D
(first valid write)
OE
D
4
t
ENS
4295 drw 08
t
SKEW1
t
FRL(1)
t
OLZ
t
OE
t
A
t
A
NOTES:
1. When t
SKEW1
minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW1
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
.
The Latency Timing applies only at the Empty Boundary (
EF = LOW).
2. The first word is available the cycle after
EF goes HIGH, always.
3. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered
EF
(IDT Standard Mode)
Figure 7. Read Cycle Timing with Single Register-Buffered
EF
(IDT Standard Mode)
14
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
D
0
- D
17
WEN
RCLK
EF
Q
0
- Q
17
OE
t
DS
t
ENS
t
A
t
SKEW1
DATA WRITE 1
DATA READ
t
ENH
t
REF
t
DS
t
ENS
DATA WRITE 2
t
ENH
t
REF
REN
DATA IN OUTPUT REGISTER
t
FRL
(1)
LOW
4295 drw 10
t
REF
t
SKEW1
t
FRL
(1)
NOTES:
1. When t
SKEW1
minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW1
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2 * t
CLK
+ t
SKEW1
, or t
CLK
+ t
SKEW1
. The
Latency Timing apply only at the Empty Boundary (
EF = LOW).
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
FF may not change state until the next WCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
DATA READ
WCLK
D
0
- D
17
WEN
RCLK
FF
Q
0
- Q
17
t
A
t
WFF
DATA WRITE
REN
t
WFF
t
ENH
t
ENS
t
DS
t
WFF
t
DS
DATA
WRITE
NEXT DATA READ
t
A
NO WRITE
NO WRITE
DATA IN OUTPUT REGISTER
OE
LOW
t
SKEW1
(1)
t
SKEW1
(1)
t
ENH
t
ENS
4295 drw 09
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
15
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAE
t
ENS
t
PAEA
n + 1 words in FIFO
(2),
n + 2 words in FIFO
(3)
n words in FIFO
(2),
n + 1 words in FIFO
(3)
RCLK
t
PAEA
REN
4295 drw 13
n words in FIFO
(2),
n + 1 words in FIFO
(3)
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
RCLK
t
CLK
t
ENS
t
ENH
LD
REN
Q
0
--Q
15
PAE OFFSET
PAF OFFSET
PAE OFFSET
UNKNOWN
t
A
t
ENS
4295 drw 12
t
CLKH
t
CLKL
WCLK
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENH
LD
WEN
D
0
--D
15
t
DS
t
DH
PAE OFFSET
PAF OFFSET
D
0
--D
11
PAE OFFSET
t
ENS
4295 drw 11
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
Figure 12. Read Programmable Registers (IDT Standard Mode)
16
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
RCLK
REN
4295 drw 15
D/2 words in FIFO
(2)
,
[
+ 1
]
words in FIFO
(3)
D-1
2
D/2 + 1 words in FIFO
(2)
,
[
+ 2
]
words in FIFO
(3)
D-1
2
D/2 words in FIFO
(2)
,
[
+ 1
]
words in FIFO
(3)
D-1
2
t
HF
t
HF
t
CLKL
t
CLKH
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
(1)
4295 drw 14
D - m words
in FIFO
D - (m + 1) words in FIFO
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
17
RXI
RCLK
t
t
XI
XIS
4295 drw 19
WXI
WCLK
t
XI
t
XIS
4295 drw 18
NOTE:
1. Read from Last Physical Location.
RCLK
REN
RXO
Note 1
4295 drw 17
t
XO
t
XO
t
CLKH
t
ENS
NOTE:
1. Write to Last Physical Location.
WCLK
WEN
WXO
Note 1
4295 drw 16
t
XO
t
CLKH
t
ENS
t
XO
Figure 17. Read Expansion Out Timing
Figure 16. Write Expansion Out Timing
Figure 18. Write Expansion In Timing
Figure 19. Read Expansion In Timing
18
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 20. Write Timing with Synchronous Programmable Flags (FWFT Mode)
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[
D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
- D
17
RCLK
t
DH
t
DS
t
ENS
t
SKEW1
REN
Q
0
- Q
17
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
WFF
W
[D-m+2]
W
1
t
ENH
4295 drw 20
DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
1
D-1
2
+1
]
[
W
D-1
+2
]
[
W
2
D-1
+3
]
[
W
2
t
PAFS
NOTES:
1.
t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge for
OR
to go LOW after two RCLK cycles plus t
REF
. If the time between the rising edge of WLCK and the rising edge of RCLK is less than
t
SKEW1
, then the
OR
deassertion may be delayed one extra RCLK cycle.
2.
t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for
PAE
to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less tha
n
t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
3.
LD
= HIGH,
OE
= LOW
4
.
n =
PAE
offset, m =
PAF
offset, D = maximum FIFO depth = 257 words for the IDT72V805, 513 words for the IDT72V815, 1,025 words for the IDT72V825, 2,04
9 words for the IDT72V835 and 4,097 words for the IDT72V845.
5
.
Select this mode by setting (
FL
,
RXI
,
WXI
) = (1,0,1) during Reset.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
Figure 21. Read Timing with Synchronous Programmable Flags (FWFT Mode)
WCLK
12
WEN
D
0
- D
17
RCLK
t
ENS
REN
Q
0
- Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
t
OHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
OE
t
A
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
OE
t
SKEW2
W
D
4295 drw 21
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
t
HF
t
REF
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
1
t
ENS
D-1
+ 1
]
[
W
2
D-1
+ 2
]
[
W
2
NOTES:
1.
t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
IR
will go LOW after one WCLK plus t
WFF
. If the time between the rising edge of RLCK and the rising edge of WCLK is
less than t
SKEW1
, then the
IR
assertion may be delayed an extra WCLK cycle.
2.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge for
PAF
to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less th
an
t
SKEW2,
then the
PAF
deassertion time may be delayed an extra WCLK cycle.
3.
LD
= HIGH
4
.
n =
PAE
offset, m =
PAF
offset, D = maximum FIFO depth = 257 words for the IDT72V805, 513 words for the IDT72V815, 1,025 words for the IDT72V825, 2,04
9 words for IDT72V835 and 4,097 words for IDT72V845.
5
.
Select this mode by setting (
FL
,
RXI
,
WXI
) = (1,0,1) during Reset.
20
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
t
ENH
WEN
PAE
RCLK
REN
4295 drw 22
t
ENS
t
ENH
t
ENS
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
SKEW2
t
PAES
n Words in FIFO
(2)
,
n + 1 words in FIFO
(3)
(4)
t
PAES
n words in FIFO
(2)
,
n + 1words in FIFO
(3)
t
CLKH
t
CLKL
WCLK
t
ENH
WEN
PAF
RCLK
REN
4295 drw 23
t
ENS
t
ENH
t
ENS
D - m Words in FIFO
D -(m+1) Words
in FIFO
t
SKEW2
(3)
t
PAFS
t
PAFS
D-(m+1) Words in
FIFO
t
CLKL
t
CLKH
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for
PAE to go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (
FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3. t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge for
PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than t
SKEW2
, then the
PAF deassertion time may be delayed an extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (
FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
21
D
0
- D
17
WEN
RCLK
FF
REN
t
ENH
t
ENH
Q
0
- Q
17
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
DATA WRITE
4295 drw 24
WCLK
NO WRITE
1
2
1
2
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
A
t
ENS
t
DS
t
A
Wd
(1)
(1)
t
ENS
t
SKEW1
t
SKEW1
WCLK
D
0
-
D
17
WEN
FF
RCLK
REN
t
WFF
t
WFF
DATAIN VALID
NO OPERATION
(1)
t
SKEW1
4295 drw 25
t
ENH
1
2
t
CLKH
t
CLKL
t
CLK
t
DS
t
DH
t
ENS
Figure 25. Write Cycle Timing with Double Register-Buffered
FF
(IDT Standard Mode)
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus t
WFF
. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then the
FF deassertion time may be delayed an extra WCLK cycle.
2.
LD = HIGH.
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus t
RFF
. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than t
SKEW1
. then the
FF deassertion may be delayed an extra WCLK cycle.
2.
LD = HIGH
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
22
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle plus t
REF
. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than t
SKEW1
. then the
EF deassertion may be delayed an extra RCLK cycle.
2.
LD = HIGH
3. Select this mode by setting (
FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered
EF
(IDT Standard Timing)
NO OPERATION
RCLK
REN
EF
t
CLKL
t
ENH
t
REF
LAST WORD
t
A
t
OLZ
t
OE
Q
0
-
Q
17
OE
WCLK
(1)
WEN
4295 drw 26
D
0
-
D
17
t
ENS
t
ENS
t
ENH
t
DS
FIRST WORD
t
OHZ
1
2
t
CLK
t
CLKH
t
REF
t
SKEW1
t
DH
W
1
W
2
W
4
W
[n +2]
W
[n+3]
WCLK
WEN
D
0
-
D
17
RCLK
t
DH
t
DS
t
SKEW1
REN
Q
0
-
Q
17
t
DS
t
A
t
REF
OR
W
1
DATA IN OUTPUT REGISTER
(1)
W
3
1
2
3
t
ENH
t
REF
4295 drw 27
t
ENS
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge for
OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the
rising edge of RCLK is less than t
SKEW1
, then the
OR deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH, OE = LOW
3. Select this mode by setting (
FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Figure 27.
OR
Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
23
Figure 29. Block Diagram of the Two FIFOs Contained in One IDT72V805/72V815/72V825/72V835/72V845
Configured for a 36-Bit Width Expansion
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN
)
READ CLOCK (RCLK)
READ ENABLE (
REN
)
LOAD (
LD
)
OUTPUT ENABLE (
OE
)
DATA IN (D)
DATA OUT (Q)
FULL FLAG/INPUT
READY (
FF
/
IR
)
PROGRAMMABLE (
PAE
)
HALF FULL FLAG (
HF
)
EMPTY FLAG/OUTPUT
READY (
EF
/
OR
)
PROGRAMMABLE (
PAF
)
RESET (
RS
)
FIFO A
FIFO B
RESET (
RS
)
36
36
18
18
18
18
FF
/
IR
EF
/
OR
4295 drw 29
FL
WXI RXI
FL
WXI RXI
FF
/
IR
EF
/
OR
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN
)
READ CLOCK (RCLK)
READ ENABLE (
REN
)
LOAD (
LD
)
OUTPUT ENABLE (
OE
)
DATA IN (D
0
- D
17
)
DATA OUT (Q
0
- Q
17
)
FULL FLAG/INPUT READY (
FF
/
IR
)
PROGRAMMABLE (
PAE
)
HALF-FULL FLAG (
HF
)
EMPTY FLAG/OUTPUT READY (
EF
/
OR
)
PROGRAMMABLE (
PAF
)
RESET (
RS
)
IDT
72V805
72V815
72V825
72V835
72V845
4295 drw 28
FL
RXI
WXI
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72V805/72V815/
72V825/72V835/72V845 may be used as a stand-alone device when the
application requirements are for 256/512/1,024/2,048/4,096 words or less.
These FIFOs are in a single Device Configuration when the First Load (
FL),
Write Expansion In (
WXI) and Read Expansion In (RXI) control inputs are
configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(one of the two FIFOs contained in the IDT72V805/72V815/72V825/72V835/72V845)
NOTE:
1. Do not connect any output control signals directly together.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two
IDT72V805/72V815/72V825/72V835/72V845s. Any word width can be
attained by adding additional IDT72V805/72V815/72V825/72V835/72V845s.
These FIFOs are in a single Device Configuration when the First Load (
FL),
Write Expansion In (
WXI) and Read Expansion In (RXI) control inputs are
configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 29). Please see the Application Note AN-83.
24
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags
Used in Depth Expansion Configuration
DEPTH EXPANSION CONFIGURATION -- DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72V805/72V815/72V825/72V835/72V845s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (
FL)
control input.
2. All other devices must have
FL in the HIGH state.
3. The Write Expansion Out (
WXO) pin of each device must be tied to the
Write Expansion In (
WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (
RXI) pin of the next device. See Figure 30
5. All Load (
LD) pins are tied together.
6. The Half-Full flag (
HF) is not available in this Depth Expansion
Configuration.
7.
EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite
PAE
and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72V805/72V815/72V825/72V835/72V845
devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down") until
it finally appears at the outputs of the last FIFO in the chainno read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN
DATA OUT
RESET
FIRST LOAD (
FL
)
Vcc
WXOA
WXIA
RXOA
RXIA
WXOB
WXIB
RXOB
RXIB
IDT72V845
FFA
/
IRA
PAFA
EFA
/
ORA
PAEA
PAFB
PAEB
EF
PAE
FF
PAF
4295 drw 30
RCLKB
RENB
OEB
WCLKB
WENB
RSB
FLA
RCLKA
RENA
OEA
WCLKA
WENA
RSA
LDA
DAn
QAn
DBn
QBn
LDB
FIFO A
4,096 x 18
FIFO B
4,096 x 18
FFA
/
IRA EFA
/
ORA
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
25
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
4295 drw 31
n
n
n
RXI
HF
72V805
72V815
72V825
72V835
72V845
WXI
FL
V
CC
GND
(0,1)
72V805
72V815
72V825
72V835
72V845
RXI
WXI
FL
V
CC
GND
(0,1)
PAF
HF
PAE
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory
with Programmable Flags Used in Depth Expansion Configuration
For an empty expansion configuration, the amount of time it takes for
OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO's outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N 1)*(4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and T
RCLK
is the RCLK
period. Note that extra cycles should be added for the possibility that the
t
SKEW1
specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the
OR flag.
The "ripple down" delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's
IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N 1)*(3*transfer clock) + 2 T
WCLK
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK
period. Note that extra cycles should be added for the possibility that the
t
SKEW1
specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
26
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
BLANK
Commercial (0
C to +70
C)
Industrial (-40
C to +85
C)
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Process /
Temperature
Range
4295 drw 32
Com'l & Ind'l
I
(1)
PF
Thin Quad Flatpack (TQFP, PK128-1)
10
15
20
Commercial Only
Commercial Only
L
Low Power
72V805
72V815
72V825
72V835
72V845
256 x 18
3.3V Dual Synchronous FIFO
512 x 18
3.3V Dual Synchronous FIFO
1,024 x 18
3.3V Dual Synchronous FIFO
2,048 x 18
3.3V Dual Synchronous FIFO
4,096 x 18
3.3V Dual Synchronous FIFO
NOTE:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DATASHEET DOUCUMENT HISTORY
04/26/2001
pgs. 1, 4, 5 and 26.
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for SALES:
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fax: 408-492-8674
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PFPkg: www.idt.com/docs/PSC4045.pdf