2002 Integrated Device Technology, Inc. All rights reserves. Product specifications subject to change without notice.

DSC-5712/4

DECEMBER 2002

3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
2,048 x 2,048

IDT72V90823

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.

FUNCTIONAL BLOCK DIAGRAM

RX0

RX1

RX2
RX3

RX4

RX5
RX6

RX7

ODE

F0i

DS/
RD

A0-A7

GND

CCO

DTA D8-D15/

AD0-AD7

RX8
RX9

RX10

RX11
RX12

RX13

RX14
RX15

TX0
TX1

TX2

TX3
TX4

TX5
TX6

TX7

TX8
TX9

TX10
TX11

TX12

TX13
TX14

TX15

AS/
ALE

CLK

FE/
HCLK

WFPS

TDI

TMS

TCK

TDO

TRST

RESET

5712 drw01

Receive
Serial Data
Streams

Output
MUX

Loopback

Test Port

Data Memory

Internal
Registers

Microprocessor Interface

Timing Unit

Connection
Memory

Transmit
Serial Data
Streams

FEATURES:

2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s

Per-channel variable or constant throughput delay

Automatic identification of ST-BUS

/GCI interfaces

Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s

Automatic frame offset delay measurement

Per-stream frame delay offset programming

Per-channel high impedance output control

Per-channel Processor Mode

Control interface compatible to Intel/Motorola CPUs

Connection memory block programming

IEEE-1149.1 (JTAG) Test Port

Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack

(PQFP) and 100-pin Thin Quad Flatpack (TQFP)

3.3V Power Supply

Operating Temperature Range -40

°°
°°
°C to +85°°°°°C

DESCRIPTION:

The IDT72V90823 is a non-blocking digital switch that has a capacity of

2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels
at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. Some of the main features
are: programmable stream and channel control, Processor Mode, input offset
delay and high-impedance output control.

Per-stream input delay control is provided for managing large multi-chip

switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

PIN CONFIGURATIONS

83 82 81

39 40 41 42 43 44 45

INDEX

5712 drw03

80 79 78 77 76 75

11 10 9

46 47 48 49 50 51 52

33 34 35 36 37 38

CCO
DTA
D15

D14

D13

D12

D11

D10

GND

VCC

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

RX8

RX9

RX10

RX11

RX12

RX13

RX14

RX15

F0i

FE/HCLK

GND

CLK

VCC

TMS

TDI

TDO

TCK

TRST

RESET

WFPS

DS/

/
RW

AS/ALE

GND

TX15

TX14

TX13

TX12

TX11

TX10

TX9

TX8

VCC

GND

TX7

TX6

TX5

TX4

TX3

TX2

TX1

TX0

ODE

GND

RX0

RX2

RX7

RX10

RX5

RX11

RX13

RX14

FOI

TMS

TX13

RX1

RX8

RX9

RX4

RX12

RX15

FE/

HCLK

TDI

TDO

TX11

TX14

RX6

VCC

RX3

VCC

CLK

TCK

TRST

TX10

TX12

VCC

D11

D14

CCO

D13

ODE

TX0

D10

DTA

TX2

TX3

VCC

TX5

TX4

GND

TX6

TX7

GND

TX9

TX8

A1 BALL PAD CORNER

D12

AD5

AD3

AD0

AS/ALE

DNC

GND

VCC

GND

VCC

D15

AD7

AD6

AD2

DS/RD

TX1

VCC

AD4

AD1

W/RW

VCC

GND

VCC

TX15

GND

VCC

RESET

WFPS

5712 drw02

BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)

TOP VIEW

PLCC: 0.05in. pitch, 1.15in. x 1.15in. (PL84-1, order code: J)

TOP VIEW

NOTES:
1. DNC - Do Not Connect
2. IC - Internal Connection, tie to GROUND for normal operation.
3. All I/O pins are 5V tolerant except for TMS, TDI and

TRST.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

INDEX

5712 drw04

100

DNC

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

RX8

RX9

RX10

RX11

RX12

RX13

RX14

RX15

F0i

FE/HCLK

GND

CLK

VCC

CCO

DTA

D15

D14

D13

D12

D11

D10

GND

VCC

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

DNC

TMS

TDI

TDO

TCK

TRST

RESET

WFPS

DS/

/
RW

AS/ALE

GND

TX15

TX14

TX13

TX12

TX11

TX10

TX9

TX8

VCC

GND

TX7

TX6

TX5

TX4

TX3

TX2

TX1

TX0

ODE

GND

DNC

PIN CONFIGURATIONS (CONTINUED)

INDEX

5712 drw05

RX0

RX1

RX2

RX3

RX4

RX5

RX6

RX7

RX8

RX9

RX10

RX11

RX12

RX13

RX14

RX15

FOi

FE/HCLK

CLK

DTA

D15

D14

D13

D12

D11

D10

GND

VCC

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

DNC

VCC

TMS

TDI

TDO

TCK

TRST

RESET

WFPS

DS/

/
WR

AS/ALE

DNC

GND

TX15

TX14

TX13

TX12

TX11

TX10

TX9

TX8

VCC

GND

TX7

TX6

TX5

TX4

TX3

TX2

TX1

TX0

ODE

GND

CCO

DNC

GND

100

PQFP: 0.65mm pitch, 14mm x 20mm (PQ100-2, order code: PQF)

TOP VIEW

TQFP: 0.50mm pitch, 14mm x 14mm (PN100-1, order code: PF)

TOP VIEW

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

PIN DESCRIPTION

SYMBOL

NAME

I/O

DESCRIPTION

GND

Ground.

Ground Rail.

Vcc

+3.3 Volt Power Supply.

TX0-15

(1)

TX Output 0 to 15

Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon

(Three-state Outputs)

the value programmed at bits DR0-1 in the IMS register.

RX0-15

(1)

RX Input 0 to 15

Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.

F0i

(1)

Frame Pulse

When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted

according to ST-BUS

and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame

pulse which conforms to WFPS formats.

FE/HCLK

(1)

Frame Evaluation/

When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK

HCLK Clock

(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.

CLK

(1)

Clock

Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed
at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.

TMS

Test Mode Select

JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.

TDI

Test Serial Data In

JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.

TDO

Test Serial Data Out

JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.

TCK

(1)

Test Clock

Provides the clock to the JTAG test logic.

TRST

Test Reset

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V90823 is in the normal functional mode.

(1)

Internal Connection

Connect to GND for normal operation. This pin must be low for the IDT72V90823 to function normally and to comply

with IEEE 1114 (JTAG) boundary scan requirements.

RESET

(1)

Device Reset

This input (active LOW) puts the IDT72V90823 in its reset state that clears the device internal counters, registers

(Schmitt Trigger Input)

and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the

RESET

pin must be held LOW for a minimum of 100ns to reset the device.

WFPS

(1)

Wide Frame

When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in

Pulse Select

ST-BUS

/GCI mode.

A0-7

(1)

Address 0-7

When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.

DS/

(1)

Data Strobe/Read

For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with

to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with

CS to enable the read and write operations. For Intel multiplexed bus

operation, this input is

RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.

W / WR

(1)

Read/Write / Write

In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/

W. This input controls

the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is

WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.

(1)

Chip Select

Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V90823.

AS/ALE

(1)

Address Strobe or

This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed

Latch Enable

bus operation, connect this pin to ground.

NOTE:
1. These pins are 5V tolerant.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

(1)

CPU Interface Mode

When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.

AD0-7

(1)

Address/Data Bus

I/O

These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins

0 to 7

are also the input address bits of the microprocessor port.

D8-15

(1)

Data Bus 8-15

I/O

These pins are the eight most significant data bits of the microprocessor port.

DTA

(1)

Data Transfer

This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin

Acknowledgment

drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.

CCO

(1)

Control Output

This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The
level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section.

ODE

(1)

Output Drive Enable

This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.

PIN DESCRIPTION (CONTINUED)

SYMBOL

NAME

I/O

DESCRIPTION

NOTE:
1. These pins are 5V tolerant.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

FUNCTIONAL DESCRIPTION

The IDT72V90823 is capable of switching up to 2,048 x 2,048, 64 Kbit/s

PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.

The serial input streams of the IDT72V90823 can have a bit rate of 2.048,

4.096 or 8.192 Mb/s and are arranged in 125

µs wide frames, which contain

32, 64 or 128 channels respectively. The data rates on input and output streams
are identical.

In Processor Mode, the microprocessor can access input and output time-

slots on a per channel basis allowing for transfer of control and status information.
The IDT72V90823 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS

or GCI

formats.

With the variety of different microprocessor interfaces, IDT72V90823 has

provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/

W/WR, DS/RD, AS/ALE).

The frame offset calibration function allows users to measure the frame offset

delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 11.

The internal loopback allows the TX output data to be looped around to the

RX inputs for diagnostic purposes.

A functional Block Diagram of the IDT72V90823 is shown in Figure 1.

DATA AND CONNECTION MEMORY

The received serial data is converted to parallel format by internal serial-

to-parallel converters and stored sequentially in the data memory. The 8 KHz
input frame pulse (

F0i) is used to generate channel and frame boundaries of

the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 2,048 bytes.

Data to be output on the serial streams (TX0-15) may come from either the

data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.

CONNECTION AND PROCESSOR MODES

In the Connection Mode, the addresses of the input source data for all output

channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 13 and Table 14. Once the source address bits are
programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then
onto a TX output stream.

By having the each location in the connection memory specify an input

channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.

In Processor Mode, the microprocessor writes data to the connection

memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.

As the IDT72V90823 can be used in a wide variety of applications, the device

also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V90823 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.

If an output channel is set to a high-impedance state through the connection

memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS

outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.

The connection memory data can be accessed via the microprocessor

interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 4, 6 and 7).

SERIAL DATA INTERFACE TIMING

The master clock frequency must always be twice the data rate. For serial

data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data
rates will always be identical.

The IDT72V90823 provides two different interface timing modes ST-BUS

GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V90823
is in the wide frame pulse (WFP) frame alignment mode.

In ST-BUS

/GCI mode, the input 8 KHz frame pulse can be in either

ST-BUS

or GCI format. The IDT72V90823 automatically detects the presence

of an input frame pulse and identifies it as either ST-BUS

or GCI. In ST-BUS

format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.

WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING

When the device is in WFP frame alignment mode, the CLK input must be

at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse
is in ST-BUS

format. The timing relationship between CLK, HCLK and the frame

pulse is shown in Figure 9.

When WFPS pin is high, the frame alignment evaluation feature is disabled.

However, the frame input offset registers may still be programmed to compensate
for the varying frame delays on the serial input streams.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 1

-- SWITCHING CONFIGURATION

SWITCHING CONFIGURATIONS

The IDT72V90823 can operate at different speeds. To configure the

maximum non-blocking switching data rate, the two DR bits in the IMS register
are used. Following are the possible configurations:

2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with

16-input/16-output data streams each having 32, 64 Kbit/s channels each. This
mode requires a CLK of 4.096 MHz and allows a maximum non-blocking
capacity of 512 x 512 channels.

4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with

16-input/16-output data streams each having 64, 64 Kbit/s channels each. This
mode requires a CLK of 8.192 MHz and allows a maximum non-blocking
capacity of 1,024 x 1,024 channels.

8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with

16-input/16-output data streams each having 128, 64 Kbit/s channels each. This
mode requires a CLK of 16.384 MHz and allows a maximum non-blocking
capacity of 2,048 x 2,048 channels.

Table 1 summarizes the switching configurations and the relationship

between different serial data rates and the master clock frequencies.

INPUT FRAME OFFSET SELECTION

Input frame offset selection allows the channel alignment of individual input

streams to be offset with respect to the output stream channel alignment (i.e.

F0i).

Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.

Each input stream can have its own delay offset value by programming the

frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of 1/2 clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 11 and 12 for delay offset
programming.

SERIAL INPUT FRAME ALIGNMENT EVALUATION

The IDT72V90823 provides the frame evaluation (FE) input to determine

different data input delays with respect to the frame pulse

F0i.

A measurement cycle is started by setting the start frame evaluation (SFE)

bit low for at least one frame. When the SFE bit in the IMS register is changed

from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.

In ST-BUS

mode, the falling edge of the frame measurement signal (FE)

is evaluated against the falling edge of the ST-BUS

frame pulse. In GCI mode,

the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 10 & Figure 4 for the description of the frame alignment register.

This feature is not available when the WFP Frame Alignment mode is

enabled (i.e., when the WFPS pin is connected to VCC).

MEMORY BLOCK PROGRAMMING

The IDT72V90823 provides users with the capability of initializing the entire

connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 9 of the IMS register.

The block programming mode is enabled by setting the memory block

program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.

LOOPBACK CONTROL

The loopback control (LPBK) bit of each connection memory location allows

the TX output data to be looped backed internally to the RX input for diagnostic
purposes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.

DELAY THROUGH THE IDT72V90823

The switching of information from the input serial streams to the output serial

streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.

The delay through the device varies according to the type of throughput

delay selected in the

V/C bit of the connection memory.

VARIABLE DELAY MODE (

V/C BIT = 0)

In this mode, the delay is dependent only on the combination of source and

destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V90823 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the IDT72V90823 in the
variable delay mode.

Serial Interface

Master Clock Required

Matrix Channel

Data Rate

(MHz)

Capacity

2.048 Mb/s

4.096

512 x 512

4.096 Mb/s

8.192

1,024 x 1,024

8.192 Mb/s

16.384

2,048 x 2,048

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

CONSTANT DELAY MODE (

V/C BIT = 1)

In this mode, frame integrity is maintained in all switching configurations by

making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V90823, the minimum throughput delay achievable in the constant
delay mode will be one frame. For example, in 2 Mb/s mode, when input time-
slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots of
delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame.
See Table 3.

MICROPROCESSOR INTERFACE

The IDT72V90823 provides a parallel microprocessor interface for multi-

plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.

If the IM pin is low a Motorola non-multiplexed bus should be connected to

the device. If the IM pin is high, the device monitors the AS/ALE and DS/

RD to

determine what mode the IDT72V90823 should operate in.

If DS/

RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed

timing is selected. If DS/

RD is high at the rising edge of AS/ALE, then the mode

2 multiplexed bus timing is selected.

For multiplexed operation, the required signals are the 8-bit data and

address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/

RD), Read/Write /Write (R/W / WR),

Chip select (

CS) and Data transfer acknowledge (DTA). See Figure 12 and

Figure 13 for multiplexed parallel microport timing.

For the Motorola non-multiplexed bus, the required signals are the 16-bit

data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(

CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed

microport timing.

The IDT72V90823 microport provides access to the internal registers,

connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.

MEMORY MAPPING

The address bus on the microprocessor interface selects the internal

registers and memories of the IDT72V90823.

If the A7 address input is low, then A6 through A0 are used to address the

interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
used to select 32, 64, or 128 locations corresponding to data rate of the ST-
BUS

. The address input lines and the stream address bits (STA) of the control

register allow access to the entire data and connection memories. The control
and IMS registers together control all the major functions of the device, see
Figure 3.

As explained in the Serial Data Interface Timing and Switching Configura-

tions sections, after system power-up, the IMS register should be programmed
immediately to establish the desired switching configuration.

The data in the control register consists of the memory block programming

bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the

entire connection memory block to be programmed. The memory select bit is
used to designate the connection memory or the data Memory. The stream
address bits select internal memory subsections corresponding to input or output
serial streams.

The data in the IMS register consists of block programming bits (BPD0-

BPD4), block programming enable bit (BPE), output stand by bit (OSB), start
frame evaluation bit (SFE) and data rate selection bits (DR0-1). The block
programming and the block programming enable bits allows users to program
the entire connection memory (see Memory Block Programming section). If the
ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS

output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and
all TX output drivers are enabled.

CONNECTION MEMORY CONTROL

The CCO pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512,

1,024 or 2,048 bits, respectively. The contents of the CCO bit of each connection
memory location are output on the CCO pin once every frame. The contents
of the CCO bits of the connection memory are transmitted sequentially on to the
CCO pin and are synchronous with the data rates on the other serial streams.

The CCO bit is output one channel before the corresponding channel on

the serial streams. For example, in 2.048 Mb/s mode (32 channels per frame),
the contents of the CCO bit in position 0 (TX0, CH0) of the connection memory
is output on the first clock cycle of channel 31 through CCO pin. The contents
of the CCO bit in position 32 (TX1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CCO pin.

If the ODE pin or the OSB bit is high, the OE bit of each connection memory

location controls the output drivers-enables (if high) or disables (if low). See
Table 5 for detail.

The processor channel (PC) bit of the connection memory selects between

Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.

The

V/C (Variable/Constant Delay) bit in each connection memory location

allows the per-channel selection between variable and constant throughput
delay modes.

If the LPBK bit is high, the associated TX output channel data is internally

looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.

INITIALIZATION OF THE IDT72V90823

After power up, the state of the connection memory is unknown. As such,

the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

Connection Memory

Data Memory

Control Register

CRb7

5712 drw06

10000000

The Control Register is only accessed when A7-A0 are all
zeroed. When A7 =1, up to 128 bytes are randomly accessa-
ble via A0-A6 at any one instant. Of which stream these
bytes (channels) are accessed is determined by the state of
CRb3 -CRb0.

CRb6 CRb5 CRb4

CRb2 CRb1 CRb0

CRb4

Stream

CRb2 CRb1 CRb0

CRb3

Channel 127
Channel 127

Channel 127
Channel 127
Channel 127
Channel 127
Channel 127

Channel 127
Channel 127

Channel 127
Channel 127
Channel 127
Channel 127
Channel 127

Channel 127

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

Channel 0

Channel 1

Channel 2

10000001

10000010

11111111

External Address Bits

A7-A0

Figure 3. Addressing Internal Memories

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 3

-- CONSTANT THROUGHPUT DELAY VALUE

TABLE 4

-- INTERNAL REGISTER AND ADDRESS MEMORY MAPPING

TABLE 2

-- VARIABLE THROUGHPUT DELAY VALUE

Delay for Constant Throughput Delay Mode

Input Rate

(m output channel number)

(n input channel number)

2.048 Mb/s

32 + (32 n) + m time-slots

4.096 Mb/s

64 + (64 n) + m time-slots

8.192 Mb/s

128 + (128 n) + m time-slots

Delay for Variable Throughput Delay Mode

Input Rate

(m output channel number)

(n input channel number)

m < n

m = n, n+1, n+2

m > n+2

2.048 Mb/s

32 (n-m) time-slots

m-n + 32 time slots

m-n time-slots

4.096 Mb/s

64 (n-m) time-slots

m-n + 64 time-slots

m-n time slots

8.192 Mb/s

128 (n-m) time-slots

m-n + 128 time-slots

m-n time-slots

(1)

Location

Control Register, CR

Interface Mode Selection Register, IMS

Frame Alignment Register, FAR

Frame Input Offset Register 0, FOR0

Frame Input Offset Register 1, FOR1

Frame Input Offset Register 2, FOR2

Frame Input Offset Register 3, FOR3

Ch0

Ch1

Ch30

Ch31

(Note 2)

Ch32

Ch33

Ch62

Ch63

(Note 3)

Ch64

Ch65

Ch126

Ch127

(Note 4)

Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.

2. Channels 0 to 31 are used when serial interface is at 2.048 Mb/s mode
3. Channels 0 to 63 are used when serial interface is at 4.096 Mb/s mode.

4. Channels 0 to 127 are used when serial interface is at 8.192 Mb/s mode.

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 6

-- CONTROL REGISTER (CR) BITS

TABLE 7

-- VALID ADDRESS LINES FOR DIFFERENT BIT RATES

TABLE 5

-- OUTPUT HIGH IMPEDANCE CONTROL

OE bit in Connection

ODE pin

OSB bit in IMS

TX Output Driver

Memory

Register

Status

Don't Care

Per Channel

High-Impedance

Enable

Read/Write Address:

Reset Value:

0000

MBP

STA3

STA2

STA1

STA0

Bit

Name

Description

15-6

Unused

Must be zero for normal operation.

MBP

When 1, the connection memory block programming feature is ready for the programming of Connection

(Memory Block Program)

Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.

When 0, connection memory is selected for read or write operations. When 1, the data memory is selected

(Memory Select)

for read operations and connection memory is selected for write operations.

(No microprocessor write operation is allowed for the data memory.)

3-0

STA3-0

The binary value expressed by these bits refers to the input or output data stream, which corresponds

(Stream Address Bits)

to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB)

Input/Output

Valid Address Lines

Data Rate

2.048 Mb/s

A4, A3, A2, A1, A0

4.096 Mb/s

A5, A4, A3, A2, A1, A0

8.192 Mb/s

A6, A5, A4, A3, A2, A1, A0

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 8

-- INTERFACE MODE SELECTION (IMS) REGISTER BITS

TABLE 9

-- SERIAL DATA RATE SELECTION (16 INPUT X 16 OUTPUT)

DR1

DR0

Data Rate Selected

Master Clock Required

2.048 Mb/s

4.096 MHz

4.096 Mb/s

8.192 MHz

8.192 Mb/s

16.384 MHz

Reserved

Read/Write Address:

Reset Value:

0000

Bit

Name

Description

15-10

Unused

Must be zero for normal operation.

9-5

BPD4-0

These bits carry the value to be loaded into the connection memory block whenever the memory block

(Block Programming Data)

programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.

BPE

A zero to one transition of this bit enables the memory block programming function. The BPE and

(Begin Block Programming

BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set

Enable)

HIGH, the device requires two frames to complete the block programming. After the programming function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.

OSB

When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When

(Output Stand By)

ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15

output drivers function normally.

SFE

A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR

(Start Frame Evaluation)

cycle, set this bit to zero for at least one frame.

1-0

DR0-1

Input/Output data rate selection. See Table 9 for detailed programming.

(Data Rate Select)

BPD4 BPD3 BPD2 BPD1 BPD0

BPE

OSB

SFE

DR1

DR0

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

ST-BUS

Frame

CLK

Offset Value

FE Input

GCI Frame

CLK

Offset Value

FE Input

(FD[10:0] = 06

)

(FD11 = 0, sample at CLK LOW phase)

(FD[10:0] = 09

)

(FD11 = 1, sample at CLK HIGH phase)

5712 drw07

TABLE 10

-- FRAME ALIGNMENT REGISTER (FAR) BITS

Figure 4. Example for Frame Alignment Measurement

Bit

Name

Description

15-13

Unused

Must be zero for normal operation.

CFE

When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment

(Complete Frame Evaluation)

offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.

FD11

The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)

(Frame Delay Bit 11)

or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.

10-0

FD10-0

The binary value expressed in these bits refers to the measured input offset value. These bits are rest to

(Frame Delay Bits)

zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 MSB, FD0 LSB)

Read/Write Address:

Reset Value:

0000

CFE

FD11

FD10

FD9

FD8

FD7

FD6

FD5

FD4

FD3

FD2

FD1

FD0

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 11

-- FRAME INPUT OFFSET REGISTER (FOR) BITS

NOTE:
1. n denotes an input stream number from 0 to 15.

Name

(1)

Description

OFn2, OFn1, OFn0

These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to

(Offset Bits 2, 1 & 0)

start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the

F0i input of the device. See Figure 5.

DLEn

(Data Latch Edge)

ST-BUS

mode:

DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.

GCI mode:

DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.

Read/Write Address:

for FOR0 register,

for FOR1 register,

for FOR2 register,

for FOR3 register,

Reset Value:

0000

for all FOR registers.

OF32

OF31

OF30

DLE3

OF22

OF21

OF20

DLE2

OF12

OF11

OF10

DLE1

OF02

OF01

OF00

DLE0

FOR0 Register

OF72

OF71

OF70

DLE7

OF62

OF61

OF60

DLE6

OF52

OF51

OF50

DLE5

OF42

OF41

OF40

DLE4

FOR1 Register

OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10

OF92

OF91

OF90

DLE9

OF82

OF81

OF80

DLE8

FOR2 Register

OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12

FOR3 Register

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

TABLE 13

-- CONNECTION MEMORY BITS

TABLE 14

-- CAB BIT PROGRAMMING FOR DIFFERENT DATA RATES

NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel

and stream associated with this location.

Bit

Name

Description

LPBK

When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback

(Per Channel Loopback)

operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.

V/C

This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a

(Variable/Constant

per-channel basis.

Throughput Delay)

When 1, the contents of the connection memory are output on the corresponding output channel and stream.

(Processor Channel)

Only the lower byte (bit 7 bit 0) will be output to the TX output pins. When 0, the contents of the connection
memory are the data memory address of the switched input channel and stream.

CCO

This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.

(Control Channel Output)

This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions

(Output Enable)

normally. When 0, the output driver is in a high-impedance state.

10-8,7

(1)

SAB3-0

The binary value is the number of the data stream for the source of the connection.

(Source Stream Address Bits)

6-0

(1)

CAB6-0

The binary value is the number of the channel for the source of the connection.

(Source Channel Address Bits)

LPBK

V/C

CCO

SAB3

SAB2

SAB1

SAB0

CAB6

CAB5

CAB4

CAB3

CAB2

CAB1

CAB0

Data Rate

CAB Bits Used to Determine the Source Channel of the Connection

2.048 Mb/s

CAB4 to CAB0 (32 channel/input stream)

4.096 Mb/s

CAB5 to CAB0 (64 channel/input stream)

8.192 Mb/s

CAB6 to CAB0 (128 channel/input stream)

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

JTAG SUPPORT

The IDT72V90823 JTAG interface conforms to the Boundary-Scan stan-

dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan Test (BST). The operation of the boundary-scan
circuitry is controlled by an external test access port (TAP) Controller.

TEST ACCESS PORT (TAP)

The Test Access Port (TAP) provides access to the test functions of the

IDT72V90823. It consists of three input pins and one output pin.

·Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with

any on-chip clock and thus remain independent. The TCK permits shifting of test
data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.

·Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP

Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not
driven from an external source.

·Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register

or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vcc when it is not driven from an external source.

·Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the

contents of either the instruction register or data register are serially shifted out
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through the boundary scan cells, the TDO
driver is set to a high impedance state.

·Test Reset (

TRST)

Reset the JTAG scan structure. This pin is internally pulled to VCC.

INSTRUCTION REGISTER

In accordance with the IEEE 1149.1 standard, the IDT72V90823 uses

public instructions. The IDT72V90823 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
the instructions are decoded to achieve two basic functions: to select the test data
register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during
data register scanning. See Table below for Instruction decoding.

Value Instruction

Function

000 EXTEST

Select Boundary Scan Register

001 EXTEST

Select Boundary Scan Register

010 Sample/preload

Select Boundary Scan Register

011 Sample/preload

Select Boundary Scan Register

100 Sample/preload

Select Boundary Scan Register

101 Sample/preload

Select Boundary Scan Register

110 Bypass

Select Bypass Register

111 Bypass

Select Bypass Register

TEST DATA REGISTER

As specified in IEEE 1149.1, the IDT72V90823 JTAG Interface contains two

test data registers:

·The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells

arranged to form a scan path around the boundary of the IDT72V90823 core
logic.

·The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit

path from TDI to its TDO. The IDT72V90823 boundary scan register contains
118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out.
All three-state enable bits are active high.

JTAG Instruction Register Decoding

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

RECOMMENDED DC OPERATING
CONDITIONS

DC ELECTRICAL CHARACTERISTICS

NOTE:
1.

Voltages are with respect to ground unless other wise stated.

NOTE:
1. Outputs Unloaded.
2. For TDI, TMS, and TRST pins, the maximum leakage current is 50

µA.

Test Point

Output

GND

VCC

GND

5712 drw09

Symbol

Parameter

Min.

Typ.

Max.

Units

Positive Supply

3.0

3.6

Input HIGH Voltage (3.3V)

2.0

Input HIGH Voltage (5.0V)

2.0

5.5

Input LOW Voltage

GND

0.8

Operating Temperature

-40

+85

°C

Commercial

Symbol

Characteristics

Min.

Typ.

Max.

Units

(1)

Supply Current

@ 2.048 Mb/s

@ 4.096 Mb/s

@ 8.192 Mb/s

(2)

Input Leakage (input pins)

µA

Input Leakage (I/O pins)

µA

Input Pin Capacitance

High-impedance Leakage

µA

Output HIGH Voltage

2.4

Output LOW Voltage

0.4

Output Pin Capacitance

Figure 6. Output Load

S1 is open circuit except when testing output
levels or high impedance states.

S2 is switched to V

or GND when testing

output levels or high impedance states.

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

-0.3

5.0

Voltage on Digital Inputs (3.3V)

GND -0.3

+0.3

Voltage on Digital Inputs (5.0V)

GND -0.3

5.5

Current at Digital Outputs

Storage Temperature

-65

+125

° C

Package Power Dissapation

NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under

these conditions is not implied.

ABSOLUTE MAXIMUM RATINGS

(1)

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK

NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

Symbol

Characteristics

Min.

Typ.

Max.

Units

FPW

Frame Pulse Width (ST-BUS

, GCI)

Bit rate = 2.048 Mb/s

295

Bit rate = 4.096 Mb/s

145

Bit rate = 8.192 Mb/s

FPS

Frame Pulse Setup time before CLK falling (ST-BUS

or GCI)

FPH

Frame Pulse Hold Time from CLK falling (ST-BUS

or GCI)

CLK Period

Bit rate = 2.048 Mb/s

190

300

Bit rate = 4.096 Mb/s

110

150

Bit rate = 8.192 Mb/s

CLK Pulse Width HIGH

Bit rate = 2.048 Mb/s

150

Bit rate = 4.096 Mb/s

Bit rate = 8.192 Mb/s

CLK Pulse Width LOW

Bit rate = 2.048 Mb/s

150

Bit rate = 4.096 Mb/s

Bit rate = 8.192 Mb/s

, t

Clock Rise/Fall Time

HFPW

Wide Frame Pulse Width

Bit rate = 8.192 Mb/s

195

295

HFPS

Frame Pulse Setup Time before HCLK falling

150

HFPH

Frame Pulse Hold Time from HCLK falling

150

HCP

HCLK (4.096 MHz) Period

Bit rate = 8.192 Mb/s

190

300

HCH

HCLK (4.096 MHz) Pulse Width HIGH

Bit rate = 8.192 Mb/s

150

HCL

HCLK (4.096 MHz) Pulse Width LOW

Bit rate = 8.192 Mb/s

150

, t

HCLK Rise/Fall Time

DIF

Delay between falling edge of HCLK and falling edge of CLK

-10

Symbol

Characteristics

Min.

Typ.

Max.

Unit

Test Conditions

SIS

RX Setup Time

SIH

RX Hold Time

SOD

TX Delay Active to Active

= 30pF

= 200pF

TX Delay Active to High-Z

= 1K

, C

= 200pF

TX Delay High-Z to Active

= 1K

, C

= 200pF

ODE

Output Driver Enable (ODE) Delay

= 1K

, C

= 200pF

XCD

CCO Output Delay

= 30pF

= 200pF

AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS

(1)

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

ALW

ALE

5712 drw15

ADDRESS

DATA

CSRW

ALRD

CSR

CSW

DHW

DHR

AKH

DDR

DSW

SWD

ALWR

AKD

AD0-AD7

D8-D15

DTA

ADS

ADH

Figure 12. Multiplexed Bus Timing (Intel Mode)

AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)

NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

ALW

ALE Pulse Width

ADS

Address Setup from ALE falling

ADH

Address Hold from ALE falling

ALRD

RD Active after ALE falling

DDR

Data Setup from

DTA LOW on Read

= 150pF

CSRW

CS Hold after RD/WR

RD Pulse Width (Fast Read)

CSR

CS Setup from RD

DHR

(1)

Data Hold after

= 150pF, R

= 1K

WR Pulse Width (Fast Write)

ALWR

WR Delay after ALE falling

CSW

CS Setup from WR

DSW

Data Setup from

WR (Fast Write)

SWD

Valid Data Delay on Write (Slow Write)

122

DHW

Data Hold after

WR Inactive

AKD

Acknowledgment Delay:

Reading/Writing Registers

43/43

= 150pF

Reading/Writing Memory

@ 2.048 Mb/s

760/750

= 150pF

@ 4.096 Mb/s

400/390

= 150pF

@ 8.192 Mb/s

220/210

= 150pF

AKH

(1)

Acknowledgment Hold Time

= 150pF, R

= 1K

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

5712 drw16

ADDRESS

CSS

DSH

ASW

CSH

DDR

ADS

ADH

AD0-AD7,

D8-D15

DTA

DATA

ADDRESS

DATA

RWS

DWS

SWD

DHW

AKD

AD0-AD7,

D8-D15

RWH

AKH

DHR

AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA)

Figure 13. Multiplexed Bus Timing (Motorola Mode)

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

ASW

ALE Pulse Width

ADS

Address Setup from AS falling

ADH

Address Hold from AS falling

DDR

Data Setup from

DTA LOW on Read

= 150pF

CSH

CS Hold after DS falling

CSS

CS Setup from DS rising

DHW

Data Hold after Write

DWS

Data Setup from DS Write (Fast Write)

SWD

Valid Data Delay on Write (Slow Write)

122

RWS

W Setup from DS Rising

RWH

W Hold from DS Rising

DHR

(1)

Data Hold after Read

= 150pF, R

= 1K

DSH

DS Delay after AS falling

AKD

Acknowledgment Delay:

Reading/Writing Registers

43/43

= 150pF

Reading/Writing Memory

@ 2.048 Mb/s

760/750

= 150pF

@ 4.096 Mb/s

400/390

= 150pF

@ 8.192 Mb/s

220/210

= 150pF

AKH

(1)

Acknowledgment Hold Time

= 150pF, R

= 1K

NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

COMMERCIAL TEMPERATURE RANGE

IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048

VALID WRITE ADDRESS

A0-A7

CSS

CSH

RWS

RWH

ADS

ADH

VALID WRITE

DATA

AD0-AD7/
D8-D15

DSW

DHW

DTA

AKD

AKH

CSS

CSH

RWS

RWH

VALID READ ADDRESS

ADS

ADH

VALID READ DATA

DDR

DHR

AKD

AKH

5712 drw17

SWD

Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing

AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

CSS

CS Setup from DS falling

RWS

R/W Setup from DS falling

ADS

Address Setup from DS falling

CSH

CS Hold after DS rising

RWH

R/W Hold after DS Rising

ADH

Address Hold after DS Rising

DDR

Data Setup from DTA LOW on Read

= 150pF

DHR

Data Hold on Read

= 150pF, R

= 1K

DSW

Data Setup on Write (Fast Write)

SWD

Valid Data Delay on Write (Slow Write)

122

DHW

Data Hold on Write

AKD

Acknowledgment Delay:

Reading/Writing Registers

43/43

= 150pF

Reading/Writing Memory

@ 2.048 Mb/s

760/750

= 150pF

@ 4.096 Mb/s

400/390

= 150pF

@ 8.192 Mb/s

220/210

= 150pF

AKH

(1)

Acknowledgment Hold Time

= 150pF, R

= 1K

NOTE:
1. High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V90823

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72V90823