INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4737/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
metal CMOS technology. The ALVCH16260 is used in applications in which
two separate data paths must be multiplexed onto, or demultiplexed from, a
single data path. Typical applications include multiplexing and/or demultiplexing
address and data information in microprocessor or bus-interface applications.
This device also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA)
inputs control the bus transceiver functions. The OE1B and OE2B control
signals also allow bank control in the A-to-B direction. Address and/or data
information can be stored using the internal storage latches. The latch-enable
(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
When the latch-enable input is high, the latch is transparent. When the latch-
enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCH16260 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16260 has "bus-hold" which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads
LE1B
LEA1B
OE1B
SEL
OE A
A
1:12
LE2B
LEA2B
O E2B
A-1B
LATC H
1B-A
LATC H
A-2B
LATC H
2B-A
LATC H
M
U
X
1
0
12
12
12
12
12
12
12
1
B
1:12
2
B
1:12
12
12
30
29
2
28
1
27
55
56
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
OEA
2
B
3
GND
2
B
2
2
B
1
V
CC
A
1
A
2
GND
A
3
A
4
A
5
A
6
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
OE2B
2
B
4
GND
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
2
B
9
2
B
10
2
B
11
2
B
12
GND
1
B
11
1
B
10
1
B
9
1
B
8
GND
1
B
7
1
B
6
1
B
5
GND
1
B
3
LE2B
SEL
25
26
27
28
32
31
30
29
GND
1
B
4
LEA1B
OE1B
A
7
1
B
2
V
CC
1
B
12
LE1B
LEA2B
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
I/O
I/O Port Capacitance
V
IN
= 0V
7
9
pF
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
FUNCTION TABLES
(1)
Inputs
Output
1Bx
2Bx
SEL
LE1B
LE2B
OEA
Ax
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A
0
(2)
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A
0
(2)
X
X
X
X
X
H
Z
B-TO-A (OEB = H)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
3
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
Ax
LEA1B
LEA2B
OE1B
OE2B
1Bx
2Bx
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
2B
0
(2)
L
H
L
L
L
L
2B
0
(2)
H
L
H
L
L
1B
0
(2)
H
L
L
H
L
L
1B
0
(2)
L
X
L
L
L
L
1B
0
(2)
2B
0
(2)
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
A-TO-B (OEA = H)
FUNCTION TABLES
(CONTINUED)
(1)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Pin Names
I/O
Description
Ax
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's address/data bus.
(1)
1
Bx
(1:12)
I/O
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
(1)
2
Bx
(1:12)
I/O
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
(1)
LEA1B
I
Latch Enable Input for A-1B Latch. The latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA1B.
LEA2B
I
Latch Enable Input for A-2B Latch. The latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LEA2B.
LE1B
I
Latch Enable Input for 1B-A Latch. The latch is open when LE1B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LE1B.
LE2B
I
Latch Enable Input for 2B-A Latch. The latch is open when LE2B is HIGH. Data from the A-port is latched on the HIGH to LOW
transition of LE2B.
SEL
I
1B or 2B Port Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from
2B Port to A Port.
OEA
I
Output Enable for A Port (Active LOW)
OE1B
I
Output Enable for 1B Port (Active LOW)
OE2B
I
Output Enable for 2B Port (Active LOW)
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
5
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
37
41
pF
C
PD
Power Dissipation Capacitance Outputs disabled
4
7
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PLH
Propagation Delay
1
5.4
--
5.1
1.2
4.3
ns
t
PHL
Ax to 1Bx or Ax to 2Bx
t
PLH
Propagation Delay
1
5.4
--
5.1
1.2
4.3
ns
t
PHL
1Bx to Ax or 2Bx to Ax
t
PLH
Propagation Delay
1
5.6
--
5.2
1
4.4
ns
t
PHL
LEXB to Ax
t
PLH
Propagation Delay
1
5.6
--
5.2
1
4.4
ns
t
PHL
LE1B to 1BX or LEA2B to 2Bx
t
PLH
Propagation Delay
1
6.9
--
6.6
1.1
5.6
ns
t
PHL
SEL to Ax
t
PZH
Output Enable Time
1
6.7
--
6.4
1
5.4
ns
t
PZL
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
t
PHZ
Output Disable Time
1
5.7
--
5
1.3
4.6
ns
t
PLZ
OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx
t
SU
Set-up Time, data before LE1B, LE2B, LEA1B, LEA2B
1.4
--
1.1
--
1.1
--
ns
t
H
Hold Time, data after LE1B, LE2B, LEA1B, LEA2B
1.6
--
1.9
--
1.5
--
ns
t
W
Pulse Width, LE1B, LE2B, LEA1B, or LEA2B HIGH
3.3
--
3.3
--
3.3
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALV C Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW -HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
7
ORDERING INFORMATION
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PV
PA
PF
16
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
12-Bit to 24-Bit Multiplexed D-Type Latch with 3-State
Outputs
40C to +85C
X
XX
Family
Bus-Hold
260
Bus-Hold
Double-Density, 24mA
H
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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