INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4538/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
Balanced Output Drivers: 12mA
Low switching noise
IDT74ALVCH162821
3.3V CMOS 20-BIT
BUS-INTERFACE FLIP-
FLOP WITH 3-STATE OUT-
PUTS AND BUS-HOLD
C
1
1
D
TO 9 OTHER CHAN NELS
1
OE
1
56
1
CLK
1
D
1
55
1
Q
1
2
One of 10
Channels
C
1
1
D
TO 9 OTHER CHAN NELS
2
OE
28
29
2
CLK
2
D
1
42
2
Q
1
15
One of 10
Channels
DESCRIPTION:
This 20-bit bus-interface flip-flop is built using advanced CMOS technology.
The ALVCH162821 device can be used as two 10-bit flip-flops or one 20-bit
flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the device provides true data at the Q outputs.
A buffered output-enable (
OE) input can be used to place the ten outputs in
either a normal logic state (high or low logic levels) or a high-impedance state.
In the high impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without the need for interface or pullup components.
OE input does not affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the high-impedance
state.
The ALVCH162821 has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive 12mA at the designated threshold levels.
The ALVCH162821 has "bus-hold" which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
FUNCTION TABLE
(EACH 10-BIT FLIP-FLOP)
(1)
Pin Names
Description
xDx
Data Inputs
(1)
xCLK
Clock Input
x Q x
3-State Outputs
xOE
3-State Output Enable Inputs (Active LOW)
PIN DESCRIPTION
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
OUT
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
1
OE
1
Q
1
GND
1
Q
2
V
CC
1
Q
5
1
Q
6
GND
1
Q
7
1
Q
8
1
Q
9
1
Q
10
1
Q
4
2
Q
1
GND
2
Q
2
2
Q
3
2
Q
4
V
CC
2
Q
5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
1
CLK
GND
V
CC
GND
GND
2
Q
9
GND
2
Q
7
2
OE
25
26
27
28
32
31
30
29
GND
2
Q
8
1
Q
3
2
Q
6
V
CC
2
Q
10
2
D
9
2
D
10
2
CLK
2
D
8
2
D
7
2
D
6
2
D
5
2
D
4
2
D
3
2
D
1
1
D
10
2
D
2
1
D
9
1
D
8
1
D
7
1
D
5
1
D
4
1
D
3
1
D
1
1
D
6
1
D
2
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Output
xOE
xCLK
xDx
xQx
L
H
H
L
L
L
L
H or L
X
Q
0
(2)
H
X
X
Z
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
3
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1.
Typical values are at V
CC
= 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1.
Pins with Bus-Hold are identified in the pin description.
2.
Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
NOTE:
1.
V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 4mA
1.9
--
I
OH
= 6mA
1.7
--
V
CC
= 2.7V
I
OH
= 4mA
2.2
--
I
OH
= 8mA
2
--
V
CC
= 3V
I
OH
= 6mA
2.4
--
I
OH
= 12mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 4mA
--
0.4
I
OL
= 6mA
--
0.55
V
CC
= 2.7V
I
OL
= 4mA
--
0.4
I
OL
= 8mA
--
0.6
V
CC
= 3V
I
OL
= 6mA
--
0.55
I
OL
= 12mA
--
0.8
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance per Flip Flop Outputs enabled
C
L
= 0pF, f = 10Mhz
40
45
pF
C
PD
Power Dissipation Capacitance per Flip Flop Outputs disabled
26
28
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
150
--
150
--
150
--
MHz
t
PLH
Propagation Delay
1
6.3
--
5.8
1
5
ns
t
PHL
xCLK to xQx
t
PZH
Output Enable Time
1
7
--
6.6
1
5.5
ns
t
PZL
xOE to xQx
t
PHZ
Output Disable Time
1
6.2
--
5.5
1
5.1
ns
t
PLZ
xOE to xQx
t
SU
Set-up Time, data before xCLK
4.7
--
4.1
--
3.6
--
ns
t
H
Hold Time, data after xCLK
0
--
0
--
0
--
ns
t
W
Pulse Duration, xCLK HIGH or LOW
3.3
--
3.3
--
3.3
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTES:
1.
See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2
Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
5
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW -HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol
V
CC
(1)
= 3.3V0.3V V
CC
(1)
= 2.7V
V
CC
(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH162821
3.3V CMOS 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
ORDERING INFORMATION
ID T
XX
ALVC
XXX
XX
Package
D evice Type
Tem p. R ange
PV
PA
PF
162
74
Shrink S m all O utline P ackage
Thin Shrink Small Outline Package
Thin Very Sm all O utline Package
20-Bit Bus-Interface Flip-Flop w ith 3-State O utputs
40C to +85C
X
XX
Fam ily
Bus-H old
821
Bus-H old
D ouble-D ensity w ith R e sistors, 12mA
H
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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