INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
1
JUNE 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4582/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads
IDT74ALVCH16901
3.3V CMOS 18-BIT
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs
for checking parity. The direction of data flow is controlled by OEAB and
OEBA. When SEL is low, the parity functions are enabled. When SEL is high,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
The ALVCH16901 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has "bus-hold" which retains the inputs' last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
1
C LKEN A B
2
C LK EN AB
LE AB
O EA B
OD D /EV EN
1
A
1
-
1
A
8
SE L
B -P ort
P arity
G enerate
and
C heck
A D ata
2
A -Port
P arity
Generate
and
C heck
B Data
18-Bit
Storage
C LKA B
1
APA R
1
E RR B
2
A
1
-
2
A
8
2
A PA R
2
E RR B
1
B
1
-
1
B
8
1
BP AR
1
E R RA
2
B
1
-
2
A
8
2
BP AR
2
E RR A
O EBA
C LKB A
1
C LKE NB A
2
C LKE NB A
LEB A
18-B it
S torage
18
18
18
18
Q
A
Q
B
2
2
1
32
3
30
5
61
28
36
34
31
63
64
33
62
29
37
35
60
4
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
TSSOP
TOP VIEW
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
OUT
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
1
CLKENAB
LEAB
CLKAB
1
ERRA
V
CC
GND
1
A
1
V
CC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
56
57
58
59
60
61
62
63
64
1
V
CC
GND
V
CC
GND
GND
25
26
27
28
40
39
38
37
2
BPAR
CLKBA
2
CLKENAB
SEL
29
30
31
32
36
35
34
33
2
CLKENBA
1
APAR
GND
1
CLKENBA
LEBA
1
ERRB
1
BPAR
GND
1
A
2
1
A
3
1
A
4
1
A
5
1
A
6
1
B
1
1
B
2
1
B
3
1
B
4
1
B
5
1
B
6
1
A
7
1
A
8
2
A
1
1
B
7
1
B
8
2
B
1
2
A
2
2
B
2
2
A
3
2
B
3
GND
GND
2
B
4
2
B
5
2
A
4
2
A
5
2
A
6
2
A
8
2
A
7
2
B
6
2
B
7
2
B
8
OEAB
2
ERRA
2
APAR
ODD/EVEN
2
ERRB
OEBA
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
xCLKENAB
A-to-B 9-bit Clock Enables
xCLKENBA
B-to-A 9-bit Clock Enables
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
xERRA
A Error-Signal Outputs
xERRB
B Error-Signal Outputs
xAPAR
A Port Parities
xBPAR
B Port Parities
ODD/EVEN
Parity Select Input
SEL
Parity Enables
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
PIN DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
3
FUNCTION TABLE
(1,2)
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
xAx
xBx
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B
(3)
L
L
L
L
L
L
L
L
H
H
L
L
L
L
X
B
(3)
L
L
L
H
X
B
(4)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
and CLKENBA.
3. Output level before the indicated steady-state conditions were established.
4. Output level before the indicated steady-state conditions were established,
provided that CLKAB was LOW before LEAB went LOW.
PARITY ENABLE
Inputs
SEL OEBA OEAB
Operation or Function
L
H
L
Parity is checked on port A and is generated on port B.
L
L
H
Parity is checked on port B and is generated on port A.
L
H
H
Parity is checked on port B and port A.
L
L
L
Parity is generated on port A and B if device is in FF
mode.
H
L
L
Parity functions are
Q
A
data to B, Q
B
data to A
H
L
H
disabled; device acts as
Q
B
data to A
H
H
L
a standard 18-bit
Q
A
data to B
H
H
H
registered transceiver.
Isolation
PARITY
Inputs
Outputs
OF INPUTS
OF INPUTS
SEL
OEBA OEAB
ODD/EVEN
A1-
--
--
-A8 = H
B1--
--
--
-B8 = H
xAPAR
xBPAR
xAPAR
xERRA
xBPAR
xERRB
L
H
L
L
0, 2, 4, 6, 8
N/A
L
N/A
N/A
H
L
Z
L
H
L
L
1, 3, 5, 7
N/A
L
N/A
N/A
L
H
Z
L
H
L
L
0, 2, 4, 6, 8
N/A
H
N/A
N/A
L
L
Z
L
H
L
L
1, 3, 5, 7
N/A
H
N/A
N/A
H
H
Z
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
L
L
Z
N/A
H
L
L
H
L
N/A
1, 3, 5, 7
N/A
L
H
Z
N/A
L
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
H
L
Z
N/A
L
L
L
H
L
N/A
1, 3, 5, 7
N/A
H
H
Z
N/A
H
L
H
L
H
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
Z
L
H
L
H
1, 3, 5, 7
N/A
L
N/A
N/A
H
L
Z
L
H
L
H
0, 2, 4, 6, 8
N/A
H
N/A
N/A
H
H
Z
L
H
L
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
L
Z
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
L
H
Z
N/A
L
L
L
H
H
N/A
1, 3, 5, 7
N/A
L
L
Z
N/A
H
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
H
H
Z
N/A
H
L
L
H
H
N/A
1, 3, 5, 7
N/A
H
L
Z
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
N/A
H
N/A
H
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
L
L
N/A
L
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
N/A
L
N/A
L
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
H
H
N/A
H
N/A
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
N/A
L
N/A
L
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
L
L
N/A
H
N/A
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
N/A
H
N/A
H
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
H
H
N/A
L
N/A
L
L
L
L
L
N/A
N/A
N/A
N/A
PE
(1)
Z
PE
(1)
Z
L
L
L
H
N/A
N/A
N/A
N/A
PO
(2)
Z
PO
(2)
Z
NOTES:
1. Parity output is set to the level so that the specific bus side is set to even parity.
2. Parity output is set to the level so that the specific bus side is set to odd parity.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1. Typical values are at V
CC
= 3.3V, +25C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
5
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
22
27
pF
C
PD
Power Dissipation Capacitance Outputs disabled
5
8
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
125
--
125
--
125
--
MHz
t
PLH
Propagation Delay
1
5.2
--
4.8
1
4.4
ns
t
PHL
xAx to xBx or xBx to xAx
t
PLH
Propagation Delay
2
8.9
--
7.6
2
6.7
ns
t
PHL
xAx to xBPAR or xBx to xAPAR
t
PLH
Propagation Delay
1
5.7
--
5.2
1
4.7
ns
t
PHL
xAPAR to xBPAR or xBPAR to xAPAR
t
PLH
Propagation Delay
2
9.7
--
8.7
2
7.5
ns
t
PHL
xAPAR to xERRA or xBPAR to xERRB
t
PLH
Propagation Delay
1.5
8.7
--
7.9
1.5
6.8
ns
t
PHL
ODD/EVEN to xERRB or xERRA
t
PLH
Propagation Delay
1.5
8.3
--
7.6
1.5
6.5
ns
t
PHL
ODD/EVEN to xAPAR or xBPAR
t
PLH
Propagation Delay
1
6.1
--
5.9
1
5.1
ns
t
PHL
SEL to xAPAR or xBPAR
t
PLH
Propagation Delay
1
6
--
5.5
1
4.8
ns
t
PHL
LEBA to xAx or LEAB to xBx
t
PLH
Propagation Delay
1.5
6.7
--
6
1.5
5.3
ns
t
PHL
LEBA to xAPAR or LEAB to xBPAR (parity feed through)
t
PLH
Propagation Delay
2.5
9.8
--
8.3
2
7.4
ns
t
PHL
LEBA to xAPAR or LEAB to xBPAR (parity generated)
t
PLH
Propagation Delay
2.5
9.9
--
8.5
2
7.5
ns
t
PHL
LEBA to xERRB or LEAB to xERRA
t
PLH
Propagation Delay
1
6.4
--
5.8
1
5.1
ns
t
PHL
CLKBA to xAx or CLKAB to xBx
t
PLH
Propagation Delay
1.5
7.1
--
6.3
1.5
5.6
ns
t
PHL
CLKBA to xAPAR or CLKAB to xBPAR(parity feed through)
t
PLH
Propagation Delay
2.5
10.2
--
8.7
2
7.7
ns
t
PHL
CLKBA to xAPAR or CLKAB to xBPAR(parity generated)
t
PLH
Propagation Delay
2.5
10.5
--
8.9
2
7.9
ns
t
PHL
CLKBA to xERRB or CLKAB to x ERRA
SWITCHING CHARACTERISTICS
(1)
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
7
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PZH
Output Enable Time
1.4
6.3
--
6.1
1
5.3
ns
t
PZL
OEAB or OEBA to xBx, xBPAR or xAx, xAPAR
t
PZH
Output Enable Time
1.4
6.2
--
5.5
1
4.9
ns
t
PZL
OEAB or OEBA to xERRA or xERRB
t
PZH
Output Enable Time
1.4
6.7
--
6.5
1
5.5
ns
t
PZL
SEL to xERRA or xERRB
t
PHZ
Output Disable Time
1.3
6.1
--
5.2
1.5
4.9
ns
t
PLZ
OEAB or OEBA to xBx, xBPAR or xAx, xAPAR
t
PHZ
Output Disable Time
1.3
7.3
--
6.5
1
5.7
ns
t
PLZ
OEAB or OEBA to xERRA or xERRB
t
PHZ
Output Disable Time
1.3
6.4
--
5.4
1.5
4.9
ns
t
PLZ
SEL to xERRA or xERRB
t
SU
Set-up Time, HIGH or LOW,
1.9
--
2
--
1.7
--
ns
xAx, xAPAR or xBx, xBPAR before CLK
t
SU
Set-up Time, HIGH or LOW,
2.1
--
2.1
--
1.7
--
ns
xCLKENAB or xCLKENBA before CLK
t
SU
Set-up Time, HIGH or LOW,
1.4
--
1.3
--
1.2
--
ns
xAx, xAPAR or xBx, xBPAR before LE
t
H
Hold Time, HIGH or LOW,
0.4
--
0.4
--
0.5
--
ns
xAx, xAPAR or xBx, xBPAR after CLK
t
H
Hold Time, HIGH or LOW,
0.5
--
0.5
--
0.7
--
ns
xCLKENAB or xCLKENBA after CLK
t
H
Hold Time, HIGH or LOW,
0.9
--
1.1
--
0.9
--
ns
xAx, xAPAR or xBx, xBPAR after LE
t
W
Pulse Width LEAB or LEBA HIGH
3
--
3
--
3
--
ns
t
W
Pulse Width CLKAB or CLKBA HIGH or LOW
3
--
3
--
3
--
ns
t
SK
(o)
Output Skew
(2)
--
--
--
--
--
500
ps
SWITCHING CHARACTERISTICS (CONTINUED)
(1)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2
Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
8
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol V
CC(1)
= 3.3V0.3V V
CC(1)
= 2.7V
V
CC(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
9
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
XX
ALVC
XXX
XX
Package
Device Type
Temp. Range
PA
16
74
Thin Shrink Small Outline Package
18-Bit Universal Bus Transceiver with
Parity Generators/Checkers
-40C to +85C
X
XXX
Family
Bus-Hold
901
Bus-Hold
Double-Density, 24mA
H
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