INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

SEPTEMBER 1999

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DSC-4911/1

FEATURES:

· 0.5 MICRON CMOS Technology
· Typical t

SK(o)

(Output Skew) < 250ps

· ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

· V

= 3.3V ± 0.3V, Normal Range

· V

= 2.7V to 3.6V, Extended Range

· V

= 2.5V ± 0.2V

· CMOS power levels (0.4

µµ
µµ
µ W typ. static)

· Rail-to-Rail output swing for increased noise margin
· Available in SSOP, TSSOP, and TVSOP packages

APPLICATIONS:

· 3.3V high speed systems
· 3.3V and lower voltage computing systems

DRIVE FEATURES:

· High Output Drivers: ±24mA
· Suitable for heavy loads

IDT74ALVCH16903

3.3V CMOS 12-BIT UNIVERSAL

BUS DRIVER WITH PARITY

CHECKER, DUAL 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

This 12-bit universal bus driver is built using advanced dual metal CMOS

technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The YERR output, which is
produced one cycle after APAR, is open drain.

MODE selects one of the two data paths. When MODE is low, the device

operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (CLKEN) input is low, data setup at the
A inputs is stored in the internal registers. On the positive transition of CLK and
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internal registers. When MODE is high, the device operates as a buffer and data
at the A inputs passes directly to the outputs. The 11A/YERREN serves a dual
purpose; it acts as a normal data bit and also enables YERR data to be clocked
into the YERR output register.

When used as a single device, parity output enable (PAROE) must be tied

high; when parity input/output (PARI/O) is low, even parity is selected and when
PARI/O is high, odd parity is selected. When used in pairs and PAROE is low,
the parity sum is output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and PAROE is high, PARI/O accepts a partial parity sum
from the first ALVCH16903.

A buffered output-enable (OE) input can be used to place the 24 outputs and

YERR in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.

The ALVCH16903 has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining speed
performance.

The ALVCH16903 has "bus-hold" which retains the inputs' last state

whenever the input bus goes to a high-impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.

Symbol

Description

Max

Unit

TERM

(2)

Terminal Voltage with Respect to GND

0.5 to +4.6

TERM

(3)

Terminal Voltage with Respect to GND

0.5 to V

+0.5

(Outputs Only)

STG

Storage Temperature

65 to +150

°C

OUT

DC Output Current

50 to +50

Continuous Clamp Current,

±50

< 0 or V

> V

Continuous Clamp Current, V

< 0

Continuous Current through each

±100

or GND

ABSOLUTE MAXIMUM RATINGS

(1)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

terminals.

3. This value is limited to 4.6V maximum.

NOTE:
1. As applicable to the device type.

Symbol

Parameter

(1)

Conditions

Typ.

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

OUT

I/O Port Capacitance

= 0V

CAPACITANCE

= +25°C, F = 1.0MHz)

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

FUNCTIONAL BLOCK DIAGRAM

M OD E

CLK

1A-12A,
APAR

CLKE N

(9A-12A, APAR)

(1A-11A/Y ERREN, A PAR)

PAR OE

(1A-12A)

Flip
Flop

Parity
Check

XOR

D Q

(1A-10A)

APA R

APAR

(11A/YERR EN)

YER R

PARI/O

1Y2-12Y2

1Y1-12Y1

(1A-8A)
8

FUNCTION TABLE

(1)

Inputs

Outputs

MODE

CLKEN

CLK

1Yx-8Yx

9Yx-12Yx

(2)

NOTES:
1. H = HIGH Voltage Level

L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH Transition

2. Output level before the indicated steady-state conditions were established.

PARITY FUNCTION TABLE

(1)

Inputs

Output

PAROE

(2)

11A/

PARI/O

OF INPUTS APAR YERR

YERREN

(3)

1A-10A= H

0, 2, 4, 6, 8, 10

1, 3, 5, 7, 9

0, 2, 4, 6, 8, 10

1, 3, 5, 7, 9

0, 2, 4, 6, 8, 10

1, 3, 5, 7, 9

0, 2, 4, 6, 8, 10

1, 3, 5, 7, 9

NOTES:
1. H = HIGH Voltage Level

L = LOW Voltage Level
X = Don't Care

2. When used as a single device, PAROE must be tied HIGH.
3. Valid after appropriate number of clock pulses have set internal register.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

SSOP/ TSSOP/ TVSOP

TOP VIEW

PIN CONFIGURATION

GND

CLK

11A/YERREN

11Y

12A

12Y

APAR

YERR

GND

10Y

MODE

10A

PARI/O

GND

10Y

PAROE

CLKEN

PARI/O FUNCTION TABLE

(1)

Inputs

Output

PAROE

OF INPUTS

APAR

PARI/O

1A-10A = H

0, 2, 4, 6, 8,10

1, 3, 5, 7, 9

0, 2, 4, 6, 8, 10

1, 3, 5, 7, 9

NOTE:
1. This table applies to the first device of a cascaded pair of ALVCH16903 devices.

NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

Pin Names

I/O

Description

1A-12A

Data Inputs

(1)

1Y1-12Y2

3-State Data Outputs

CLK

Clock Input

CLKEN

Clock Enable Input (Active LOW)

MODE

Select Pin

YERREN

Error Signal Output Enable (Active LOW)

PAROE

Parity Output Enable (Active LOW)

PARI/O

I/O

Parity Input/Output

YERR

Error Signal (Open Drain)

Output Enable Input (Active LOW)

APAR

Parity Input

PIN DESCRIPTION

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

Symbol

Parameter

Test Conditions

Min.

Typ.

(1)

Max.

Unit

Input HIGH Voltage Level

= 2.3V to 2.7V

1.7

= 2.7V to 3.6V

Input LOW Voltage Level

= 2.3V to 2.7V

0.7

= 2.7V to 3.6V

0.8

Input HIGH Current

= 3.6V

= V

± 5

µA

Input LOW Current

= 3.6V

= GND

± 5

OZH

High Impedance Output Current

= 3.6V

= V

± 10

µA

OZL

(3-State Output pins)

= GND

± 10

µA

YERR Output

= 0V to 3.6V

= V

± 10

µA

(2)

High Impedance Output Current

= 3.6V

= V

or GND

± 10

µA

Clamp Diode Voltage

= 2.3V, I

= 18mA

0.7

1.2

Input Hysteresis

= 3.3V

100

CCL

CCH

Quiescent Power Supply Current

= 3.6V, V

= GND or V

0.1

µA

CCZ

Quiescent Power Supply

One input at V

- 0.6V, other inputs at V

or GND

750

µA

Current Variation

Control Inputs

= 3.3V

= V

or GND

5.5

Data Inputs

5.5

YERR Output

= 3.3V

= V

or GND

Data Outputs

Cio

PARI/O

= 3.3V

= V

or GND

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T

= 40°C to +85°C

NOTES:
1. Typical values are at V

= 3.3V, +25°C ambient.

2. For I/O ports, the parameter I

includes the input leakage current.

BUS-HOLD CHARACTERISTICS

Symbol

Parameter

(1)

Test Conditions

Min.

Typ.

(2)

Max.

Unit

BHH

Bus-Hold Input Sustain Current

= 3V

= 2V

µA

BHL

= 0.8V

BHH

Bus-Hold Input Sustain Current

= 2.3V

= 1.7V

µA

BHL

= 0.7V

BHHO

Bus-Hold Input Overdrive Current

= 3.6V

= 0 to 3.6V

±500

µA

BHLO

NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V

= 3.3V, +25°C ambient.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

OUTPUT DRIVE CHARACTERISTICS, xYx PORTS

Symbol

Parameter

Test Conditions

(1)

Min.

Max.

Unit

= 2.3V to 3.6V

= 0.1mA

0.2

= 2.3V

= 6mA, V

= 1.7V

Output HIGH Voltage

= 2.3V

= 12mA, V

= 1.7V

1.7

= 2.7V

= 12mA, V

= 2V

2.2

= 3V

2.4

= 3V

= 24mA, V

= 2V

= 2.3V to 3.6V

= 0.1mA

0.2

= 2.3V

= 6mA, V

= 0.7V

0.4

Output LOW Voltage

= 12mA, V

= 0.7V

0.7

= 2.7V

= 12mA, V

= 0.8V

0.4

= 3V

= 24mA, V

= 0.8V

0.55

= 2.3V

Y Port

-12

High-Level Output Current

= 2.7V

-12

= 3V

PARI/O

-12

Y Port

-24

= 2.3V

Y Port

= 2.7V

Low-Level Output Current

PARI/O

= 3V

Y Port

YERR Output

NOTE:
1. V

and V

must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V

range.

= 40°C to + 85°C.

OUTPUT DRIVE CHARACTERISTICS FOR YERR AND PARI/O

Symbol

Parameter

Test Conditions

(1)

Min.

Max.

Unit

PARI/O

= 3V

OH =

12mA, V

= 2V

PARI/O

= 3V

OL =

12mA, V

= 0.8V

0.55

YERR Output only

= 3V

OL =

24mA

0.5

NOTE:
1. V

and V

must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V

range.

= 40°C to + 85°C.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

OPERATING CHARACTERISTICS FOR BUFFER MODE, T

= 25°C

= 2.5V ± 0.2V

= 3.3V ± 0.3V

Symbol

Parameter

Test Conditions

Typical

Unit

Power Dissipation Capacitance Outputs enabled

= 0pF, f = 10Mhz

57.5

Power Dissipation Capacitance Outputs disabled

17.5

OPERATING CHARACTERISTICS FOR REGISTER MODE, T

= 25°C

= 2.5V ± 0.2V

= 3.3V ± 0.3V

Symbol

Parameter

Test Conditions

Typical

Unit

Power Dissipation Capacitance Outputs enabled

= 0pF, f = 10Mhz

87.5

Power Dissipation Capacitance Outputs disabled

16.5

SIMULTANEOUS SWITCHING CHARACTERISTICS

(1)

Parameter

From

= 2.5V ± 0.2V

= 2.7V

= 3.3V ± 0.3V

(Input)

(Output)

Min.

Max.

Min.

Max.

Min.

Max.

Unit

PLH

CLK

1.8

6.5

6.1

1.8

PHL

1.4

5.9

5.1

1.7

4.5

NOTE:
1. All outputs switching.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

= 2.5V ± 0.2V

= 2.7V

= 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

MAX

125

MHz

PLH

Propagation Delay, Buffer Mode

4.4

4.2

1.1

3.8

PHL

xAx to xYx

PLH

Propagation Delay, Both Modes

5.7

4.9

1.4

4.4

PHL

CLK to YERR

PLH

Propagation Delay, Both Modes

1.2

8.6

7.9

1.7

6.6

PHL

CLK to PARI/O

PLH

Propagation Delay, Both Modes

6.8

5.2

1.3

4.5

PHL

CLK to PARI/O

PLH

Propagation Delay, Both Modes

5.9

5.8

1.3

4.9

PHL

Mode to xYx

PLH

Propagation Delay, Register Mode

6.1

5.5

1.2

4.8

PHL

CLK to xYx

5.9

4.9

1.2

4.6

PLH

Propagation Delay, Both Modes

3.6

4.2

1.9

OE to YERR

PHL

Propagation Delay, Both Modes

1.2

5.1

4.9

1.5

4.2

OE to YERR

PZH

Output Enable Time, Both Modes

1.1

6.5

6.4

1.4

5.4

PZL

OE to xYx

PZH

Output Enable Time, Both Modes

5.6

4.8

PZL

PAROE to PARI/O

PHZ

Output Disable Time, Both Modes

6.4

5.2

1.7

PLZ

OE to xYx

PHZ

Output Disable Time, Both Modes

3.2

3.8

1.2

3.8

PLZ

PAROE to PARI/O

Set-up Time, Register Mode, 1A-12A before CLK

1.7

1.9

1.45

Set-up Time, Buffer Mode, 1A to 10A before CLK

5.9

5.2

4.4

Set-up Time, Register Mode, APAR before CLK

1.2

1.5

1.3

Set-up Time, Buffer Mode, APAR before CLK

4.6

3.6

3.1

Set-up Time, Both Modes, PARI/O before CLK

2.4

1.7

Set-up Time, Buffer Mode, 11A/YERREN before CLK

1.9

1.6

Set-up Time, Register Mode, CLKEN before CLK

2.5

2.6

2.2

Hold Time, Register Mode, 1A-12A after CLK

0.4

0.25

0.55

Hold Time, Buffer Mode, 1A-10A after CLK

0.25

Hold Time, Register Mode, APAR after CLK

0.7

0.4

0.7

Hold Time, Buffer Mode, APAR after CLK

0.25

Hold Time, Register Mode, PARI/O after CLK

0.25

0.4

Hold Time, Buffer Mode, PARI/O after CLK

0.25

0.5

Hold Time, Buffer Mode, 11A/YERREN after CLK

0.25

0.4

Hold Time, Register Mode, CLKEN after CLK

0.25

0.5

0.4

Pulse Width, CLK

SK(O)

Output Skew

(2)

500

SWITCHING CHARACTERISTICS

(1)

NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T

= 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

Open

LOAD

GND

Pulse
Generator

D.U.T.

500

OUT

(1, 2)

ALVC Link

INPUT

PLH1

(x)

OUTPUT 1

OUTPUT 2

PHL1

(x)

PLH2

PHL2

(x)

= t

PLH2

PLH1

PHL2

PHL1

ALVC Link

SAME PHASE

INPUT TRANSITION

OPPOSITE PHASE

INPUT TRANSITION

PLH

PHL

PLH

OUTPUT

ALVC Link

DATA

INPUT

REM

TIMING

INPUT

SYNCHRONOUS

CONTROL

ALVC Link

ASYNCHRONOUS

CONTROL

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

ALVC Link

CONTROL

INPUT

PLZ

OUTPUT

NORMALLY

LOW

PZH

SWITCH

CLOSED

OUTPUT

NORMALLY

HIGH

ENABLE

DISABLE

SWITCH

OPEN

PHZ

PZL

LOAD/2

ALVC Link

TEST CIRCUITS AND WAVEFORMS

Propagation Delay

Test Circuit for All Outputs

Enable and Disable Times

Set-up, Hold, and Release Times

NOTES:
1. For t

(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t

(b) OUTPUT1 and OUTPUT2 are in the same bank.

DEFINITIONS:
C

= Load capacitance: includes jig and probe capacitance.

= Termination resistance: should be equal to Z

OUT

of the Pulse Generator.

NOTES:
1. Pulse Generator for All Pulses: Rate

1.0MHz; t

2.5ns; t

2.5ns.

2. Pulse Generator for All Pulses: Rate

1.0MHz; t

2ns; t

2ns.

Output Skew - t

(

)

Pulse Width

NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

Symbol V

CC(1)

= 3.3V±0.3V V

CC(1)

= 2.7V

CC(2)

= 2.5V±0.2V

Unit

LOAD

2 x Vcc

2.7

Vcc

1.5

Vcc

/ 2

300

150

300

150

TEST CONDITIONS

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

LOAD

Enable Low

Disable High

GND

Enable High

All Other Tests

Open

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

INPUT

2.7V

1.5V

DATA

INPUT

2.7V

1.5V

TIMING

INPUT

1.5V

2.7V

Output

1.5V

PHL

Input

PLH

Open

GND

500

= 30 pF

(see Note 1)

From Output

Under Test

TEST

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

GND

YERR

tPHL (see Note 8)
tPLH (see Note 9)

6V
6V

OUTPUT

CONTROL

(low-level enabling)

PLZ

PZH

OUTPUT

WAVEFORM 2

S1 at GND (see Note 2)

1.5V

PZL

1.5V

2.7V

-0.3V

1.5V

OL+

0.3V

PHZ

OUTPUT

W AVEFORM 1

S1 at 6V (see N ote 2)

1.5V

2.7V

1.5V

PARAMETER MEASUREMENT INFORMATION

= 2.7V AND 3.3V ± 0.3V

NOTES:
1. C

includes probe and jig capacitance.

2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

3. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, Z

= 50

, tr

2 ns, tf

2 ns.

4. The outputs are measured one at a time with one transition per measurement.
5. t

PLZ

and t

PHZ

are the same as t

dis

6. t

PZL

and t

PZH

are the same as t

7. t

PLH

and t

PHL

are the same as t

8. t

PHL

is measured at 1.5V.

9. t

PLH

is measured at V

+0.3V.

Load Circuit

Voltage Waveforms

Pulse Duration

Voltage Waveforms

Setup and Hold Times

Voltage Waveforms

Enable and DisableTimes

Voltage Waveforms

Propagation Delay Times

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

INPU T

CC/2

CC /2

DATA

INPU T

C C

C C/2

CC/2

TIM ING

INPUT

CC/2

Output

O H

P HL

Input

PLH

Open

GND

500

= 30 pF

(see Note 1)

2 x V

From Output

Under Test

TEST

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

2 x V

GND

YERR

tPHL (see Note 8)
tPLH (see Note 9)

2 x V

INPUT

CONTROL

(low-level

enabling)

PLZ

P ZH

OU TPUT

W AVEFOR M 2

S1 at GND

(see Note 2)

PZL

Vcc

-0.15V

Vcc

OL+

0.15V

PHZ

OUTPUT

W AVEFORM 1

S1 at 2xVcc

(see Note 2)

PARAMETER MEASUREMENT INFORMATION

= 2.5V ±

0.2V

NOTES:
1. C

includes probe and jig capacitance.

2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

3. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, Z

= 50

, tr

2 ns, tf

2 ns.

4. The outputs are measured one at a time with one transition per measurement.
5. t

PLZ

and t

PHZ

are the same as t

dis

6. t

PZL

and t

PZH

are the same as t

7. t

PLH

and t

PHL

are the same as t

8. t

PHL

is measured at V

/2.

9. t

PLH

is measured at V

+ 0.15V.

Load Circuit

Voltage Waveforms

Pulse Duration

Voltage Waveforms

Setup and Hold Times

Voltage Waveforms

Enable and DisableTimes

Voltage Waveforms

Propagation Delay Times

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER

O L

O utput

O H

PH L

Input

PLH

= 10

= 30 pF

(see Note 1)

From O utput

Under Test

Output

PH L

Input

PLH

Test
Point

CL = 0.6 pF
(see Note 1)

PARI/O of
second
ALVCH16903

ZO = 52

Td = 63 ps

From Output

Under Test

PARI/O

PARAMETER MEASUREMENT INFORMATION

= 2.5V ±

0.2V

Load Circuit

NOTES:
1. C

includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, Zo = 50, tr 2 ns, tf 2ns.

3. t

PLH

and t

PHL

are the same as t

Voltage Waveforms

Propagation Delay Times

Voltage Waveforms

Propagation Delay Times

NOTES:
1. C

includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, Zo = 50, tr 2 ns, tf 2ns.

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