1
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIALTEMPERATURE RANGE
JANUARY 2002
IDT74FCT16500AT/CT
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT
REGISTERED
TRANSCEIVER
DESCRIPTION:
The FCT16500T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA)
and clock (
CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates
in transparent mode when LEAB is high. When LEAB is low, the A data is latched
if
CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored
in the latch/flip-flop on the high-to-low transition of
CLKAB. OEAB performs the
output enable function on the B port. Data flow from B port to A port is similar but
uses
OEBA, LEBA and CLKBA. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT16500T are ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used as backplane
drivers.
B
1
C
D
C
D
A
1
LEAB
CLKAB
OEBA
LEBA
CLKBA
OEAB
TO 17 OTHER CHANNELS
C
D
C
D
1
30
28
27
55
2
3
54
2002 Integrated Device Technology, Inc.
DSC-5433/1
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V 10%
High drive outputs (32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25C
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
GN D
B
2
B
3
GN D
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
1 0
B
1 1
GN D
B
1 2
B
1 3
V
CC
B
1 4
GN D
CLKA B
B
1 6
B
1 5
B
1 7
GN D
B
1 8
GN D
CLKB A
OEA B
LEAB
A
1
GN D
A
2
A
3
V
CC
A
4
A
5
GN D
A
6
A
7
A
8
A
9
GN D
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GN D
A
17
LEBA
A
15
OEB A
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
Pin Names
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input (Active LOW)
CLKBA
B-to-A Clock Input (Active LOW)
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
PIN DESCRIPTION
Symbol
Description
Max
Unit
V
TERM(2)
Terminal Voltage with Respect to GND
0.5 to 7
V
V
TERM(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
CAPACITANCE
(T
A
= +25C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B
(2)
H
L
L
X
B
(3)
FUNCTION TABLE
(1, 4)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that
CLKAB was LOW before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
= HIGH-to-LOW Transition
3
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIALTEMPERATURE RANGE
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
O
Output Drive Current
V
CC
= Max., V
O
= 2.5V
(3)
50
--
180
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 3mA
2.5
3.5
--
V
IN
= V
IH
or V
IL
I
OH
= 15mA
2.4
3.5
--
V
I
OH
= 32mA
(4)
2
3
--
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 64mA
--
0.2
0.55
V
V
IN
= V
IH
or V
IL
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
IL
Input LOW Current (Input pins)
(5)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max.
--
5
500
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is 5A at T
A
= 55C.
OUTPUT DRIVE CHARACTERISTICS
4
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
1.5
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.,
V
IN
= V
CC
--
75
120
A/
Outputs Open
V
IN
= GND
MHz
OEAB =
OEBA = V
CC
or GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.,
V
IN
= V
CC
--
0.8
1.7
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz (
CLKAB)
50% Duty Cycle
OEAB =
OEBA = V
CC
LEAB = GND
V
IN
= 3.4V
--
1.3
3.2
One Bit Toggling
VIN = GND
fi = 5MHz
50% Duty Cycle
V
CC
= Max.,
V
IN
= V
CC
--
3.8
6.5
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz (
CLKAB)
50% Duty Cycle
OEAB =
OEBA = V
CC
LEAB = GND
V
IN
= 3.4V
--
8.5
20.8
(5)
Eighteen Bits Toggling
V
IN
= GND
fi = 2.5MHz
50% Duty Cycle
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
5
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIALTEMPERATURE RANGE
FCT16500AT
FCT16500CT
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Unit
f
MAX
CLKAB or CLKBA frequency
(3)
C
L
= 50pF
--
150
--
150
MHz
t
PLH
Propagation Delay
R
L
= 500
1.5
5.1
1.5
3.8
ns
t
PHL
Ax to Bx or Bx to Ax
t
PLH
Propagation Delay
1.5
5.6
1.5
4.2
ns
t
PHL
LEBA to Ax, LEAB to Bx
t
PLH
Propagation Delay
1.5
5.6
1.5
4.4
ns
t
PHL
CLKBA to Ax, CLKAB to Bx
t
PZH
Output Enable Time
1.5
6
1.5
4.8
ns
t
PZL
OEBA to Ax, OEAB to Bx
t
PHZ
Output Disable Time
1.5
5.6
1.5
4.4
ns
t
PLZ
OEBA to Ax, OEAB to Bx
t
SU
Set-up Time, HIGH or LOW
3
--
2.4
--
ns
Ax to
CLKAB, Bx to CLKBA
t
H
Hold Time, HIGH or LOW
0
--
0
--
ns
Ax to
CLKAB, Bx to CLKBA
t
SU
Set-up Time HIGH or LOW
Clock HIGH
3
--
2
--
ns
Ax to LEAB, Bx to LEBA
Clock LOW
1.5
--
1.5
--
t
H
Hold Time, HIGH or LOW
1.5
--
0.5
--
ns
Ax to LEAB, Bx to LEBA
t
W
LEAB or LEBA Pulse Width HIGH
(3)
3
--
3
--
ns
t
W
CLKAB or CLKBA Pulse Width, HIGH or LOW
(3)
3
--
3
--
ns
t
SK(o)
Output Skew
(4)
--
0.5
--
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
6
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OU T
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCH R ONOUS C ONTROL
PRES ET
CLEA R
ETC.
SYNC HRON OUS C ON TROL
t
S U
t
H
t
RE M
t
S U
t
H
PRES ET
CLEA R
CLOC K ENABLE
ETC.
HIGH-LOW -HIGH
PULSE
LOW -HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRAN SITION
3V
1.5V
0V
1.5V
V
OH
t
P LH
OUTPUT
OPPOSITE P HASE
INPUT TRAN SITION
3V
1.5V
0V
t
P LH
t
P HL
t
P HL
V
OL
CONTR OL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORM ALLY
LOW
OUTPUT
NORM ALLY
HIGH
SW ITCH
CLOSE D
SW ITCH
OPEN
V
OL
0.3V
0.3V
t
P LZ
t
P ZL
t
P ZH
t
P HZ
3.5V
0V
1.5V
1.5V
ENAB LE
DISABLE
V
OH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
7
IDT74FCT16500AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIALTEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Tem p. R ange
XX XX
Device Type
XX
Package
PV
PA
Shrink S mall Outline Package
Thin Shrink S mall O utline Package
18-Bit R egistered Transceiver
74
40C to +85C
16
Double-D ensity, 5 Volt, H igh D rive
FC T
XX X
Fam ily
500AT
500CT
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
DATA SHEET DOCUMENT HISTORY
1/21/2002
Removed Military temp grade
PDF 
ZIP