1
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1A (max.)
V
CC
= 5V 10%
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JUNE 2002
2002 Integrated Device Technology, Inc.
DSC-5438/2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT
REGISTER
DESCRIPTION:
The FCT16823T 18-bit bus interface registers are built using advanced,
dual metal CMOS technology. These high-speed, low-power registers with
clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus
interfacing in high-performance synchronous systems. The control inputs
are organized to operate the device as two 9-bit registers or one 18-bit
register. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The FCT16823T is ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used as backplane
drivers.
R
C
D
2
OE
2
CLR
2
CLKEN
2
CLK
2
D
1
2
Q
1
TO EIGHT O THE R CHANNELS
R
C
D
1
OE
1
CLR
1
CLK EN
1
CLK
1
D
1
1
Q
1
TO EIG HT OTHER CHANNELS
2
1
56
55
54
3
27
28
29
30
42
15
2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
SSOP/ TSSOP
TOP VIEW
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
2
CLR
GND
V
CC
2
Q
3
2
Q
5
2
Q
6
2
Q
4
GND
2
Q
7
2
Q
8
2
Q
9
2
OE
GND
1
Q
9
1
Q
5
1
Q
6
1
Q
7
1
Q
8
2
Q
1
2
Q
2
GND
1
Q
2
V
CC
1
CLR
1
Q
1
1
Q
3
1
Q
4
1
OE
1
CLK
1
D
1
GND
1
D
2
1
D
3
V
CC
1
D
4
1
D
5
1
D
6
1
D
7
1
D
8
1
D
9
GND
2
D
1
1
CLKEN
2
D
2
GND
2
D
4
V
CC
2
D
5
2
D
6
GND
2
D
7
2
D
8
2
D
9
2
CLK
2
D
3
2
CLKEN
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
2. Output level before indicated steady-state input conditions were established.
Inputs
Outputs
xOE
xCLR
xCLKEN
xCLK
xDx
xQx
Function
H
X
X
X
X
Z
High Z
L
L
X
X
X
L
Clear
L
H
H
X
X
Q
(2)
Hold
H
H
L
L
Z
Load
H
H
L
H
Z
L
H
L
L
L
L
H
L
H
H
FUNCTION TABLE
(1)
Pin Names
Description
xDx
Data Inputs
xCLK
Clock Inputs
xCLKEN
Clock Enable Inputs (Active LOW)
xCLR
Asynchronous Clear Inputs (Active LOW)
xOE
Output Enable Inputs (Active LOW)
xQx
3-State Outputs
PIN DESCRIPTION
3
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
IL
Input LOW Current (Input pins)
(5)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max.
--
5
500
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is 5A at T
A
= 55C.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
O
Output Drive Current
V
CC
= Max.
,
V
O
= 2.5V
(3)
50
--
180
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 3mA
2.5
3.5
--
V
IN
= V
IH
or V
IL
I
OH
= 15mA
2.4
3.5
--
V
I
OH
= 32mA
(4)
2
3
--
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 64mA
--
0.2
0.55
V
V
IN
= V
IH
or V
IL
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
OUTPUT DRIVE CHARACTERISTICS
4
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
1.5
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.,
V
IN
= V
CC
--
75
120
A/
Outputs Open
V
IN
= GND
MHz
xOE = xCLKEN = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.,
V
IN
= V
CC
--
0.8
1.7
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
V
IN
= 3.4V
--
1.3
3.2
fi = 5MHz
V
IN
= GND
50% Duty Cycle
One Bit Toggling
V
CC
= Max.,
V
IN
= V
CC
--
4.2
7.1
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
V
IN
= 3.4V
--
9.2
22.1
(5)
fi = 2.5MHz
V
IN
= GND
50% Duty Cycle
Eighteen Bits Toggling
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
5
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5. This condition is guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74 FCT16823AT
74FCT16823CT
74FCT16823ET
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
10
1.5
6
1.5
4.4
ns
t
PHL
CLK to xQx
R
L
= 500
C
L
= 300pF
(5)
1.5
20
1.5
12.5
1.5
8
R
L
= 500
t
PHL
Propagation Delay
C
L
= 50pF
1.5
14
1.5
6.1
1.5
4.4
ns
xCLR to xQx
R
L
= 500
t
PHZ
Output EnableTime
C
L
= 50pF
1.5
12
1.5
5.5
1.5
4.4
ns
t
PLZ
xOE to xQx
R
L
= 500
C
L
= 300pF
(5)
1.5
23
1.5
12.5
1.5
9
R
L
= 500
t
PHZ
Output Disable Time
C
L
= 5pF
(5)
1.5
7
1.5
5.2
1.5
3.6
ns
xOE to xQx
R
L
= 500
C
L
= 50pF
)
1.5
8
1.5
6.5
1.5
3.6
R
L
= 500
t
SU
Set-up Time HIGH or LOW, xDx to xCLK
C
L
= 50pF
3
--
2
--
1.5
--
ns
t
H
Hold Time HIGH or LOW, xDx to xCLK
R
L
= 500
1.5
--
1.5
--
0
--
ns
t
SU
Set-up Time HIGH or LOW, xCLKEN to xCLK
3
--
3
--
2.5
--
ns
t
H
Hold Time HIGH or LOW, xCLKEN to xCLK
0
--
0
--
0
--
ns
t
W
xCLK Pulse Width HIGH or LOW
6
--
3.3
--
3
(4)
--
ns
t
W
xCLR Pulse Width LOW
6
--
3.3
--
3
(4)
--
ns
t
REM
Recovery Time xCLR to xCLK
6
--
6
--
3
--
ns
t
SK
(o)
Output Skew
(3)
--
0.5
--
0.5
--
0.5
ns
6
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
D ATA
INPUT
TIM IN G
INPUT
ASYNC HR ONOUS C ONTROL
PRES ET
CLEA R
ETC .
SYNCHR ON OUS CONTROL
t
SU
t
H
t
R EM
t
SU
t
H
PRES ET
CLEA R
CLOCK ENABLE
ETC .
HIGH-LOW -H IGH
PU LSE
LOW -HIGH-LOW
PU LSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRAN SITION
3V
1.5V
0V
1.5V
V
O H
t
PLH
OU TPU T
OPPOSITE P HASE
INPUT TRAN SITION
3V
1.5V
0V
t
PL H
t
PH L
t
PH L
V
O L
CONTROL
IN PU T
3V
1.5V
0V
3.5V
0V
OUTPU T
NORM ALLY
LOW
OUTPU T
NORM ALLY
H IGH
SW ITCH
C LOSE D
SW ITC H
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
D ISABLE
V
OH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
7
IDT74FCT16823AT/CT/ET
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
XX
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
18-Bit Register
74
40C to +85C
16
Double-Density, 5 Volt, High Drive
FCT
XXX
Family
823AT
823CT
823ET
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
5/21/2002 Removed TVSOP package
6/21/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY
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