COMMERCIAL TEMPERATURE RANGE
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
1
MAY 2002
COMMERCIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5422/1
FEATURES:
IDT74FCT373A up to 30% faster than FAST
Equivalent to FAST output drive over full temperature and
voltage supply extremes
I
OL
= 48mA
CMOS power levels (1mW typ. static)
Octal transparent latch with 3-state output control
Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT373A/C
FAST CMOS OCTAL
TRANSPARENT LATCH
DESCRIPTION:
The IDT74FCT373 is an octal transparent latch built using an advanced
dual metal CMOS technology. These octal latches have 3-state outputs and
are intended for bus oriented applications. The flip-flops appear transparent
to the data when Latch Enable (LE) is high. When LE is low, the data that
meets the set-up time is latched. Data appears on the bus when the Output
Enable (OE) is low. When OE is high, the bus output is in the high-impedance
state.
LE
D
G
O
O
0
D
0
D
G
O
O
1
D
1
D
G
O
O
2
D
2
D
G
O
O
3
D
3
D
G
O
O
4
D
4
D
G
O
O
5
D
5
D
G
O
O
6
D
6
D
G
O
O
7
D
7
OE
COMMERCIAL TEMPERATURE RANGE
2
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
PIN CONFIGURATION
SOIC
TOP VIEW
2
3
1
16
15
14
11
19
18
20
17
13
12
V
CC
O
7
O
6
D
7
D
6
O
5
O
4
D
5
D
4
LE
5
6
7
4
8
9
10
D
1
O
0
D
0
O
1
D
3
O
2
D
2
O
3
GND
OE
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
V
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature under BIAS
55 to +125
C
T
STG
Storage Temperature
55 to +125
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current
120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Pin Names
Description
Dx
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
Ox
3-State Outputs
O x
Complementary 3-State Outputs
PIN DESCRIPTION
NOTE:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High Impedance
FUNCTION TABLE
(1)
Inputs
Outputs
Dx
LE
OE
Ox
H
H
L
H
L
H
L
L
X
X
H
Z
COMMERCIAL TEMPERATURE RANGE
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
V
I
= V
CC
--
--
5
V
CC
= Max.
V
I
= 2.7V
--
--
5
(4)
A
I
IL
Input LOW Current
V
I
= 0.5V
--
--
5
(4)
V
I
= GND
--
--
5
I
OZH
V
O
= V
CC
--
--
10
Off State (High Impedance)
V
CC
= Max.
V
O
= 2.7V
--
--
10
(4)
A
I
OZL
Output Current
V
O
= 0.5V
--
--
10
(4)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
--
mA
V
OH
Output HIGH Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= 32
A
V
HC
V
CC
--
V
CC
= Min
I
OH
= 300
A
V
HC
V
CC
--
V
V
IN
= V
IH
or V
IL
I
OH
= 15mA
2.4
4.3
--
V
OL
Output LOW Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
A
--
GND
V
LC
V
CC
= Min
I
OL
= 300
A
--
GND
V
LC
(4)
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA
--
0.3
0.5
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0C to +70C, V
CC
= 5.0V 5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
COMMERCIAL TEMPERATURE RANGE
4
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + fiNi)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.2
1.5
mA
V
IN
V
HC
; V
IN
V
LC
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
V
HC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
V
LC
MHz
OE = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
V
HC
--
1.7
4
mA
Outputs Open
V
IN
V
LC
fi = 10MHz
(FCT)
50% Duty Cycle
V
IN
= 3.4V
--
2
5
OE = GND
V
IN
= GND
LE = V
CC
One Bit Toggling
V
CC
= Max.
V
IN
V
HC
--
3.2
6.5
(5)
Outputs Open
V
IN
V
LC
fi = 2.5MHz
(FCT)
50% Duty Cycle
V
IN
= 3.4V
--
5.2
14.5
(5)
OE = GND
V
IN
= GND
LE = V
CC
Eight Bits Toggling
COMMERCIAL TEMPERATURE RANGE
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
5
FCT373A
FCT373C
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
5.2
1.5
4.2
ns
t
PHL
Dx to Ox
R
L
= 500
t
PLH
Propagation Delay
2
8.5
2
5.5
ns
t
PHL
LE to Ox
t
PZH
Output Enable Time
1.5
6.5
1.5
5.5
ns
t
PZL
t
PHZ
Output Disable Time
1.5
5.5
1.5
5
ns
t
PLZ
t
SU
Set-up Time HIGH or LOW, Dx to LE
2
--
2
--
ns
t
H
Hold Time HIGH or LOW, Dx to LE
1.5
--
1.5
--
ns
t
W
LE Pulse Width HIGH
5
--
5
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
COMMERCIAL TEMPERATURE RANGE
6
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; Z
O
50; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
COMMERCIAL TEMPERATURE RANGE
IDT74FCT373A/C
FAST CMOS OCTAL TRANSPARENT LATCH
7
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
Temp. Range
XXXX
Device Type
X
Package
SO
373A
373C
Small Outline IC
Octal Transparent Latch
74
0C to +70C
FCT
XX
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