MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
1
JUNE 2002
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-2630/8
FEATURES:
Std., A, C, and D grades
Low input and output leakage
1A (max.)
CMOS power levels
True TTL input and output compatibility:
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
Industrial: SOIC, SSOP, QSOP
Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL
D FLIP-FLOP WITH
CLOCK ENABLE
DESCRIPTION:
The IDT54/74FCT377T is an octal D flip-flop built using an advanced
dual metal CMOS technology. The IDT54/74FCT377T has eight edge-
triggered, D-type flip-flops with individual D inputs and O outputs. The
common buffered Clock (CP) input loads all flip-flops simultaneously when
the Clock Enable (CE) is low. The register is fully edge-triggered. The state
of each D input, one set-up time before the low-to-high clock transition, is
transferred to the corresponding flip-flop's O output. The CE input must be
stable only one set-up time prior to the low-to-high transition for predictable
operation.
CE
CP
D
CP
Q
D
0
O
0
D
CP
Q
D
1
O
1
D
CP
Q
D
2
O
2
D
CP
Q
D
3
O
3
D
CP
Q
D
4
O
4
D
CP
Q
D
5
O
5
D
CP
Q
D
6
O
6
D
CP
Q
D
7
O
7
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
2
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
LCC
TOP VIEW
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
1
2
3
4
5
7
9
6
8
10
11
12
13
14
15
16
17
18
19
20
O
6
D
7
D
6
O
5
D
5
C
E
D
0
O
0
V
C
C
O
3
G
N
D
C
P
O
4
D
4
INDEX
D
1
O
1
D
3
O
2
D
2
O
7
2
3
1
16
15
14
11
19
18
20
17
13
12
5
6
7
4
8
9
10
D
1
O
0
D
0
V
CC
O
1
D
3
O
2
D
2
O
3
GND
O
7
O
6
D
7
D
6
O
5
O
4
D
5
D
4
CP
CE
PIN DESCRIPTION
Pin Names
Description
D
0
D
7
Data Inputs
CE
Clock Enable (Active LOW)
O
0
O
7
Data Outputs
C P
Clock Pulse Input
FUNCTION TABLE
(1)
Inputs
Outputs
Operating Mode
CP
CE
D
O
Load "1"
l
h
H
Load "0"
l
l
L
Hold
h
X
No Change
H
H
X
No Change
NOTE:
1. H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L = LOW Voltage Level
l = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X = Don't Care
= LOW-to-HIGH Clock Transition
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
3
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial : T
A
= 40C to +85C, V
CC
= 5.0V 5%; Military: T
A
= 55C to +125C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
N
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
O
= GND
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 6mA MIL.
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 8mA IND.
I
OH
= 12mA MIL.
2
3
--
V
I
OH
= 15mA IND.
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 32mA MIL.
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA IND.
I
OFF
Input/Output Power Off
V
CC
= 0V, V
IN
or V
O
- 4.5V
--
--
1
A
Leakage
(5)
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power
V
CC
= Max.
--
0.01
1
mA
Supply Current
V
IN
= GND or V
CC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is 5A at T
A
= -55C.
5. This parameter is guaranted but not tested.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
4
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
2
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
CE = GND
V
IN
= GND
MHz
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
1.5
3.5
mA
Current
(6)
f
CP
= 10MHz
V
IN
= GND
CE = GND
V
IN
= 3.4V
--
2
5.5
One Bit Toggling
V
IN
= GND
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
3.8
7.3
(5)
f
CP
= 10MHz, 50% Duty Cycle
V
IN
= GND
CE = GND
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
f
i
= 2.5MHz
50% Duty Cycle
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
54FCT377T
54/74FCT377AT
54/74FCT377CT
74FCT377DT
Mil.
Ind.
Mil.
Ind.
Mil.
Ind.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH
Propagation Delay
C
L
= 50pF
2
15
2
7.2
2
8.3
2
5.2
2
5.5
2
4.4
ns
t
PHL
CP to Qx
R
L
= 500
t
SU
Set-up Time HIGH or LOW
3
--
2
--
2
--
2
--
2
--
2
--
ns
Dx to CP
t
H
Hold Time HIGH or LOW
2.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1
--
ns
Dx to CP
t
SU
Set-up Time HIGH or LOW
4
--
3.5
--
3.5
--
3.5
--
3.5
--
3
--
ns
CE to CP
t
H
Hold Time HIGH or LOW
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
0
--
ns
CE to CP
t
W
CP Pulse Width HIGH or LOW
7
--
8
--
7
--
6
--
7
--
3
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
5
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
XX
Package
X
Process
Fast CMOS Octal D Flip-Flop with Clock Enable
377T
377AT
377CT
377DT
SO
PY
Q
Industrial Options
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Industrial
MIL-STD-883, Class B
54
74
55C to +125C
40C to +85C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
6/26/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
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