MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
1
JUNE 2002
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5489/2
FEATURES:
Std., A, C, and D grades
Low input and output leakage
1A (max.)
CMOS power levels
True TTL input and output compatibility:
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
Industrial: SOIC, SSOP, QSOP
Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT543T/AT/CT/DT
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A
0
A
7
or to take data from B
0
B
7
, as indicated in the
Function Table. With CEAB low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the LEAB signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB and OEAB both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
A
1
Q
OEBA
A
2
A
3
A
4
A
5
A
6
A
7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
C EBA
LEB A
OEAB
C EAB
LEA B
DETAIL A x 7
D
LE
Q
D
LE
DETAIL A
A
0
B
0
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
2
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
2
3
1
20
19
18
15
16
9
10
A
6
A
7
B
6
B
7
23
22
24
21
17
5
6
7
4
8
A
1
OEBA
A
0
V
CC
A
2
A
5
A
3
A
4
CEBA
B
2
B
0
B
1
B
3
B
4
B
5
LEBA
13
14
11
12
CEAB
GND
LEAB
OEAB
1
2
3
4
5
7
8
6
9
10
11
12
13
14
15
16
17
18
19
20
INDEX
A
1
21
22
23
24
25
26
27
28
A
2
A
3
A
4
A
5
A
6
A
7
NC
G
N
D
N
C
NC
N
C
B
1
B
2
B
3
B
4
B
5
B
7
L
E
A
B
O
E
A
B
B
6
A
0
O
E
B
A
L
E
B
A
V
c
c
C
E
B
A
B
0
C
E
A
B
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
0
A
7
A-to-B Data Inputs or B-to-A 3-State Outputs
B
0
B
7
B-to-A Data Inputs or A-to-B 3-State Outputs
LCC
TOP VIEW
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
3
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is 5A at T
A
= 55C.
5. This parameter is guaranteed but not tested.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 6mA MIL
2.4
3.3
--
V
IN
= V
IH
or V
IL
I
OH
= 8mA IND
V
I
OH
= 12mA MIL
2
3
--
I
OH
= 15mA IND
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 48mA MIL
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
I
OL
= 64mA IND
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min, I
IN
= -18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 5%; Military: T
A
= 55C to +125C, V
CC
= 5.0V 10%
FUNCTION TABLE
(1, 2)
For A-to-B (Symmetric with B-to-A)
Latch
Output
Inputs
Status
Buffers
CEAB
LEAB
OEAB
A-to-B
B
0
B
7
H
X
X
Storing
High Z
X
H
X
Storing
X
X
X
H
X
High Z
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA
and OEBA.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
4
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
CEAB and OEAB = GND
V
IN
= GND
MHz
CEBA = V
CC
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
1.5
3.5
mA
f
CP
= 10MHz (LEAB )
V
IN
= GND
50% Duty Cycle
CEAB and OEAB = GND
CEBA = V
CC
V
IN
= 3.4V
--
2
5.5
One Bit Toggling
V
IN
= GND
at fi = 5MHz
50% duty cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
3.8
7.3
(5)
mA
f
CP
= 10MHz (LEAB )
V
IN
= GND
50% Duty Cycle
CEAB and OEAB = GND
CEBA = V
CC
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
at fi = 2.5MHz
50% duty cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
74FCT543AT
74FCT543CT
74FCT543DT
Symbol Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
6.5
1.5
5.3
1.5
4.4
ns
t
PHL
Transparant Mode
R
L
= 500
Ax to Bx or Bx to Ax
t
PLH
Propagation Delay
1.5
8
1.5
7
1.5
5
ns
t
PHL
LEBA to Ax, LEAB to Bx
t
PZH
Output Enable Time
1.5
9
1.5
8
1.5
5.4
ns
t
PZL
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
t
PHZ
Output Disable Time
1.5
7.5
1.5
6.5
1.5
4.3
ns
t
PLZ
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
t
SU
Set-up Time, HIGH or LOW
2
--
2
--
1.5
--
ns
Ax or Bx to LEBA or LEAB
t
H
Hold Time, HIGH or LOW
2
--
2
--
1.5
--
ns
Ax or Bx to LEBA or LEAB
t
W
LEBA or LEAB Pulse Width LOW
5
--
5
--
3
(3)
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
54FCT543T
54FCT543AT
54FCT543CT
Symbol Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
10
1.5
7.5
1.5
6.1
ns
t
PHL
Transparant Mode
R
L
= 500
Ax to Bx or Bx to Ax
t
PLH
Propagation Delay
1.5
14
1.5
9
1.5
8
ns
t
PHL
LEBA to Ax, LEAB to Bx
t
PZH
Output Enable Time
1.5
14
1.5
10
1.5
9
ns
t
PZL
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
t
PHZ
Output Disable Time
1.5
13
1.5
8.5
1.5
7.5
ns
t
PLZ
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
t
SU
Set-up Time, HIGH or LOW
3
--
2
--
2
--
ns
Ax or Bx to LEBA or LEAB
t
H
Hold Time, HIGH or LOW
2
--
2
--
2
--
ns
Ax or Bx to LEBA or LEAB
t
W
LEBA or LEAB Pulse Width LOW
5
--
5
--
5
--
ns
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
7
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
XX
Package
X
Process
Fast CMOS Octal Latched Transceiver
543T
543AT
543CT
543DT
SO
PY
Q
Industrial Options
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Industrial
MIL-STD-883, Class B
54
74
55C to +125C
40C to +85C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
6/24/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY
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