MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
1
JUNE 2002
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5486/2
FEATURES:
A, B, and C grades
Low input and output leakage
1A (max.)
CMOS power levels
True TTL input and output compatibility:
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
Industrial: SOIC, SSOP, QSOP
Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTER
DESCRIPTION:
The FCT821T series is built using an advanced dual metal CMOS
technology. The FCT821T series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT821T is a buffered, 10-bit wide version of the popular
FCT374T function.
The FCT821T high-performance interface family can drive large capacitive
loads, while providing low-capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes and all outputs are designed for low-
capacitance bus loading in high-impedance state.
O E
C
P
C P
TO NINE O THER CHAN NELS
23
D
0
Y
0
D
0
13
1
2
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
2
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
LCC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D
6
D
7
D
2
D
5
D
3
D
4
D
8
23
22
24
21
17
5
6
7
4
8
D
0
V
CC
CP
OE
13
14
11
12
D
1
GND
D
9
Y
6
Y
7
Y
2
Y
5
Y
3
Y
4
Y
8
Y
0
Y
1
Y
9
1
2
3
4
5
7
8
6
9
10
11
12
13
14
15
16
17
18
19
20
INDEX
D
7
21
22
23
24
25
26
27
28
D
2
D
3
D
4
D
5
D
6
D
9
D
8
NC
G
N
D
N
C
NC
N
C
Y
6
Y
2
Y
3
Y
4
Y
5
Y
8
Y
9
C
P
Y
7
D
1
D
0
O
E
V
c
c
Y
0
Y
1
Pin Name
I/O
Description
Dx
I
D Flip-Flop Data Inputs
CLR
I
When the clear input is LOW and OE is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
C P
I
Clock Pulse for the Register. Enters data into the
register on the LOW-to-HIGH transition
Y x
O
Register 3-State Outputs
EN
I
Clock Enable. When the clock enable is LOW, data
on the Dx input is transferred to the Qx input on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx inputs do not change state, regardless
of the data or clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the
OE input is LOW, the TRUE register data is present
at the Yx outputs.
PIN DESCRIPTION
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min, I
IN
= -18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 5%; Military: T
A
= 55C to +125C, V
CC
= 5.0V 10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is 5A at T
A
= 55C.
5. This parameter is guaranteed but not tested.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 6mA MIL
2.4
3.3
--
V
IN
= V
IH
or V
IL
I
OH
= 8mA IND
V
I
OH
= 12mA MIL
2
3
--
I
OH
= 15mA IND
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 32mA MIL
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA IND
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
OUTPUT DRIVE CHARACTERISTICS
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change
= LOW-to-HIGH transition
FUNCTION TABLE
(1)
Inputs
Outputs
OE
CLR
EN
Dx
CP
Qx
Yx
Function
H
H
L
L
L
Z
High Z
H
H
L
H
H
Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
H
H
H
X
X
N C
Z
Hold
L
H
H
X
X
N C
N C
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
L
H
L
L
L
L
L
H
L
H
H
H
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
4
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
= GND
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
1.5
3.5
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE = EN = GND
V
IN
= 3.4V
--
2
5.5
One Bit Toggling
V
IN
= GND
at fi = 5MHz
V
CC
= Max.
V
IN
= V
CC
--
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE = EN = GND
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
at fi = 2.5MHz
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This condition is guaranteed but not tested.
54/74FCT821AT
54FCT821BT
54/74FCT821CT
Ind.
Mil.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
10
1.5
11.5
1.5
8.5
1.5
6
1.5
7
ns
t
PHL
CP to Yx (OE = LOW)
R
L
= 500
C
L
= 300pF
(3)
1.5
20
1.5
20
1.5
16
1.5
12.5
1.5
13.5
R
L
= 500
t
SU
Set-up Time HIGH or LOW
C
L
= 50pF
4
--
4
--
3
--
3
--
3
--
ns
Dx or EN to CP
R
L
= 500
t
H
Hold Time HIGH or LOW, Dx to CP
2
--
2
--
1.5
--
1.5
--
1.5
--
ns
t
H
Hold Time HIGH or LOW, EN to CP
2
--
2
--
0
--
0
--
0
--
ns
t
PHL
Propagation Delay, CLR to Yx
1.5
14
1.5
15
1.5
9.5
1.5
8
1.5
8.5
ns
t
REM
Recovery Time, CLR to CP
6
--
7
--
6
--
6
--
6
--
ns
t
W
Clock Pulse Width, HIGH or LOW
7
--
7
--
6
--
6
--
6
--
ns
t
W
CLR Pulse Width LOW
6
--
7
--
6
--
6
--
6
--
ns
t
PZH
Output Enable Time,
C
L
= 50pF
1.5
12
1.5
13
1.5
9
1.5
7
1.5
8
ns
t
PZL
OE to Yx
R
L
= 500
C
L
= 300pF
(3)
1.5
23
1.5
25
1.5
16
1.5
12.5
1.5
13.5
R
L
= 500
t
PHZ
Output Disable Time,
C
L
= 5pF
(3)
1.5
7
1.5
8
1.5
7
1.5
6
1.5
6
ns
t
PLZ
OE to Yx
R
L
= 500
C
L
= 50pF
1.5
8
1.5
9
1.5
8
1.5
6.5
1.5
6.5
R
L
= 500
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
6
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
7
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
XX
Package
X
Process
High Performance CMOS Bus Interface Register
821AT
821BT
821CT
SO
Q
PY
Industrial Options
Small Outline IC
Quarter-size Small Outline Package
Shrink Small Outline Package
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Industrial
MIL-STD-883, Class B
54
74
55C to +125C
40C to +85C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY
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