COMMERCIAL TEMPERATURE RANGE
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
1
JUNE 2002
COMMERCIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-4603/4
FEATURES:
Equivalent to AMD's Am29841 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
IDT74FCT841A equivalent to FASTTM speed
IDT74FCT841B 25% faster than FAST
Buffered common latch enable, clear and present inputs
I
OL
= 48mA
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMD's bilopar
Am29800 series (5
A max.)
Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT74FCT800 series is built using an advanced dual metal CMOS
technology.
The IDT74FCT840 series bus interface latches are designed to elimi-
nate the extra packages required to buffer existing latches and provide extra
data width for wider address/data paths or buses carrying parity. The
IDT74FCT841 is a buffered, 10-bit wide version of the popular `373 function.
All of the IDT74FCT800 high-performance interface family are designed
for high-capacitance load drive capability, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in the high-imped-
ance state.
IDT74FCT841A/B
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCH
LE
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
OE
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
0
D
1
D
2
D
3
D
4
D
5
D
8
D
9
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
8
Y
9
COMMERCIAL TEMPERATURE RANGE
2
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
V
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature under BIAS
55 to +125
C
T
STG
Storage Temperature
55 to +125
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current
120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
FUNCTION TABLE
(1)
Inputs
Internal
Output
OE
LE
Dx
Qx
Yx
Function
H
X
X
X
Z
High Z
H
H
L
L
Z
High Z
H
H
H
H
Z
High Z
H
L
X
N C
Z
Latched (High Z)
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
N C
N C
Latched
H
L
X
L
Z
Latched (High Z)
H
L
X
H
Z
Latched (High Z)
Pin Names
I/O
Description
Dx
I
Latch Data Inputs
LE
I
Latch Enable Input. The latches are transparent when
LE is HIGH. Input data is latched on the HIGH-to-
LOW transition.
Y x
O
3-State Latch Outputs
OE
I
Output Enable Control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the outputs
Yx are in high-impedance (off) state.
PIN DESCRIPTION
NOTE:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High-Impedance
NC = No Change
SOIC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D
6
D
7
D
2
D
5
D
3
D
4
D
8
23
22
24
21
17
5
6
7
4
8
D
0
V
CC
LE
OE
13
14
11
12
D
1
GND
D
9
Y
6
Y
7
Y
2
Y
5
Y
3
Y
4
Y
8
Y
0
Y
1
Y
9
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
COMMERCIAL TEMPERATURE RANGE
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
V
I
= V
CC
--
--
5
V
CC
= Max.
V
I
= 2.7V
--
--
5
(4)
A
I
IL
Input LOW Current
V
I
= 0.5V
--
--
5
(4)
V
I
= GND
--
--
5
I
OZH
V
O
= V
CC
--
--
10
Off State (High Impedance)
V
CC
= Max.
V
O
= 2.7V
--
--
10
(4)
A
I
OZL
Output Current
V
O
= 0.5V
--
--
10
(4)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
75
120
--
mA
V
OH
Output HIGH Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= 32
A
V
HC
V
CC
--
V
CC
= Min
I
OH
= 300
A
V
HC
V
CC
--
V
V
IN
= V
IH
or V
IL
I
OH
= 24mA
2.4
4.3
--
V
OL
Output LOW Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
A
--
GND
V
LC
V
CC
= Min
I
OL
= 300
A
--
GND
V
LC
(4)
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA
--
0.3
0.5
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0C to +70C, V
CC
= 5.0V 5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
COMMERCIAL TEMPERATURE RANGE
4
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.2
1.5
mA
V
IN
V
HC
; V
IN
V
LC
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
V
HC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
V
LC
MHz
OE = GND
LE = V
CC
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
V
HC
--
1.7
4
mA
Outputs Open
V
IN
V
LC
fi = 10MHz
(FCT)
50% Duty Cycle
V
IN
= 3.4V
--
2
5
OE = GND
V
IN
= GND
LE = V
CC
One Bit Toggling
V
CC
= Max.
V
IN
V
HC
--
3.2
6.5
(5)
Outputs Open
V
IN
V
LC
fi = 2.5MHz
(FCT)
50% Duty Cycle
V
IN
= 3.4V
--
5.2
14.5
(5)
OE = GND
V
IN
= GND
LE = V
CC
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + fiNi)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
COMMERCIAL TEMPERATURE RANGE
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. This condition is guaranteed but not tested.
74FCT841A
74FCT841B
Symbol Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
9
1.5
6.5
ns
t
PHL
Dx to Yx (LE = HIGH)
R
L
= 500
C
L
= 300pF
(4)
1.5
13
1.5
13
R
L
= 500
t
PLH
Propagation Delay
C
L
= 50pF
1.5
12
1.5
8
ns
t
PHL
LE to Yx
R
L
= 500
C
L
= 300pF
(4)
1.5
16
1.5
15.5
R
L
= 500
t
PZH
Output Enable Time,
C
L
= 50pF
1.5
11.5
1.5
8
ns
t
PZL
OE to Yx
R
L
= 500
C
L
= 300pF
(4)
1.5
23
1.5
14
R
L
= 500
t
PHZ
Output Disable Time,
C
L
= 5pF
(4)
1.5
7
1.5
6
ns
t
PLZ
OE to Yx
R
L
= 500
C
L
= 50pF
1.5
18
1.5
7
R
L
= 500
t
SU
Data to LE Set-up Time
C
L
= 50pF
2.5
--
2.5
--
ns
t
H
Data to LE Hold Time
R
L
= 500
2.5
--
2.5
--
ns
t
W
LE Pulse Width HIGH
(3)
4
--
4
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL TEMPERATURE RANGE
6
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; Z
O
50; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
COMMERCIAL TEMPERATURE RANGE
IDT74FCT841A/B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
7
IDT
Temp. Range
XXXX
Device Type
X
Package
841A
841B
Bus Interface Latch
SO
Small Outline IC
74
0C to +70C
FCT
XX
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
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