1
2003 Integrated Device Technology, Inc. All rights reserved. Product specification is subject to change without notice.
DSC-6229/1
DUAL CHANNEL T1/E1/J1 LONG HAUL/
SHORT HAUL LINE INTERFACE UNIT
PRELIMINARY
IDT82V2082
FEATURES:
Dual channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43
dB@1024 KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
Single 3.3 V power supply with 5 V tolerance on digital inter-
faces
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
Software programmable or hardware selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line
Build Out)
- Line terminating impedance (T1:100
, J1:110 , E1:75 /120
)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
INDUSTRIAL TEMPERATURE RANGES APRIL 2003
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DESCRIPTION:
The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line
Interface Unit. In receive path, an Adaptive Equalizer is integrated to
remove the distortion introduced by the cable attenuation. The
IDT82V2082 also performs clock/data recovery, AMI/B8ZS/HDB3 line
decoding and detects and reports the LOS conditions. In transmit path,
there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper and LBOs.
There is one Jitter Attenuator, which can be placed in either the receive
path or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2082 supports both Single Rail and Dual Rail system interfaces.
To facilitate the network maintenance, a PRBS/QRSS generation/detec-
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detec-
tion with 2
20
-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Mul-
tiplexed interfaces and hardware control mode
Package:
IDT82V2082: 80-pin TQFP
tion circuit is integrated in the chip, and different types of loopbacks can
be set according to the applications. Four different kinds of line terminating
impedance, 75
, 100 , 110 and 120 are selectable on a per chan-
nel basis. The chip also provides driver short-circuit protection and internal
protection diode and supports JTAG boundary scanning. The chip can be
controlled by either software or hardware.
The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
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INDUSTRIAL
TEMPERATURE RANGES
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
Figure-1 Block Diagram
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
RTIPn
RRINGn
TCLKn
TDn/TDPn
TDNn
TTIPn
TRINGn
Jitter
Attenuator
PRBS Generator
IBLC Generator
TAOS
PRBS Detector
IBLC Detector
Clock
Generator
Register
Files
Software Control Interface
Pin Control
MOD
E
[1
:0
]
TE
R
M
n
R
X
TX
M
[
1:
0]
P
U
L
S
n[
3:0]
EQ
n
P
A
TTn[
1
:
0
]
J
A
[1
:0
]
MO
N
T
n
L
P
n[
1:0]
TH
Z
RC
LK
E
RP
Dn
RS
T
INT
CS
SD
O
SC
L
K
R/
W
/
WR
/SD
I
RD
/
DS
/S
CLK
E
A[
5
:
0
]
D[
7
:
0
]
One of the Two Identical Channels
Data and
Clock
Recovery
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
B8ZS/
HDB3/AMI
Decoder
Digital
Loopback
Remote
Loopback
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Waveform
Shaper/LBO
Line
Driver
Analog
Loopback
Receiver
Internal
Termination
Transmitter
Internal
Termination
TD
O
TRST
TDI
TM
S
TCK
VDDIO
VDDD
VDDA
VDDT
VDDR
JTAG TAP
G.772
Monitor
MCL
K
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INDUSTRIAL
TEMPERATURE RANGES
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
1
IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 8
2
PIN DESCRIPTION ....................................................................................................................... 9
3
FUNCTIONAL DESCRIPTION .................................................................................................... 17
3.1
CONTROL MODE SELECTION ....................................................................................... 17
3.2
T1/E1/J1 MODE SELECTION .......................................................................................... 17
3.3
TRANSMIT PATH ............................................................................................................. 17
3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17
3.3.2 ENCODER ............................................................................................................. 17
3.3.3 PULSE SHAPER .................................................................................................... 17
3.3.3.1 Preset Pulse Templates .......................................................................... 17
3.3.3.2 LBO (Line Build Out) ............................................................................... 18
3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 18
3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 22
3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 23
3.4
RECEIVE PATH ............................................................................................................... 23
3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 23
3.4.2 LINE MONITOR ...................................................................................................... 24
3.4.3 ADAPTIVE EQUALIZER......................................................................................... 24
3.4.4 RECEIVE SENSITIVITY ......................................................................................... 24
3.4.5 DATA SLICER ........................................................................................................ 24
3.4.6 CDR (Clock & Data Recovery)................................................................................ 24
3.4.7 DECODER .............................................................................................................. 24
3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 25
3.4.9 RECEIVE PATH POWER DOWN........................................................................... 25
3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 25
3.5
JITTER ATTENUATOR .................................................................................................... 26
3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 26
3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 26
3.6
LOS AND AIS DETECTION ............................................................................................. 26
3.6.1 LOS DETECTION ................................................................................................... 26
3.6.2 AIS DETECTION .................................................................................................... 28
3.7
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 29
3.7.1 TRANSMIT ALL ONES ........................................................................................... 29
3.7.2 TRANSMIT ALL ZEROS......................................................................................... 29
3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 29
3.8
LOOPBACK ...................................................................................................................... 29
3.8.1 ANALOG LOOPBACK ............................................................................................ 29
3.8.2 DIGITAL LOOPBACK ............................................................................................. 30
3.8.3 REMOTE LOOPBACK............................................................................................ 30
3.8.4 INBAND LOOPBACK.............................................................................................. 31
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 31
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 31
TABLE OF CONTENTS
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INDUSTRIAL
TEMPERATURE RANGES
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.8.4.3 Automatic Remote Loopback .................................................................. 31
3.9
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 32
3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 32
3.9.2 ERROR DETECTION AND COUNTING ................................................................ 32
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 33
3.10 LINE DRIVER FAILURE MONITORING ........................................................................... 33
3.11 MCLK AND TCLK ............................................................................................................. 33
3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 33
3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 33
3.12 MICROCONTROLLER INTERFACES ............................................................................. 34
3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 34
3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 34
3.13 INTERRUPT HANDLING .................................................................................................. 34
3.14 5V TOLERANT I/O PINS .................................................................................................. 35
3.15 RESET OPERATION ........................................................................................................ 35
3.16 POWER SUPPLY ............................................................................................................. 35
4
PROGRAMMING INFORMATION .............................................................................................. 36
4.1
REGISTER LIST AND MAP ............................................................................................. 36
4.2
REGISTER DESCRIPTION .............................................................................................. 37
4.2.1 GLOBAL REGISTERS............................................................................................ 37
4.2.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 38
4.2.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 38
4.2.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 39
4.2.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 41
4.2.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 43
4.2.7 INTERRUPT CONTROL REGISTERS ................................................................... 46
4.2.8 LINE STATUS REGISTERS ................................................................................... 49
4.2.9 INTERRUPT STATUS REGISTERS ...................................................................... 51
4.2.10 COUNTER REGISTERS ........................................................................................ 52
5
HARDWARE CONTROL PIN SUMMARY .................................................................................. 53
6
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 55
6.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 55
6.2
JTAG DATA REGISTER ................................................................................................... 56
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 56
6.2.2 BYPASS REGISTER (BR)...................................................................................... 56
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 56
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 56
7
TEST SPECIFICATIONS ............................................................................................................ 59
8
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 71
8.1
SERIAL INTERFACE TIMING .......................................................................................... 71
8.2
PARALLEL INTERFACE TIMING ..................................................................................... 72
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INDUSTRIAL
TEMPERATURE RANGES
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
Table-1
Pin Description ................................................................................................................ 9
Table-2
Transmit Waveform Value For E1 75
........................................................................ 19
Table-3
Transmit Waveform Value For E1 120
...................................................................... 19
Table-4
Transmit Waveform Value For T1 0~133 ft................................................................... 19
Table-5
Transmit Waveform Value For T1 133~266 ft............................................................... 20
Table-6
Transmit Waveform Value For T1 266~399 ft............................................................... 20
Table-7
Transmit Waveform Value For T1 399~533 ft............................................................... 20
Table-8
Transmit Waveform Value For T1 533~655 ft............................................................... 20
Table-9
Transmit Waveform Value For J1 0~655 ft ................................................................... 21
Table-10
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 21
Table-11
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 21
Table-12
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 21
Table-13
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 22
Table-14
Impedance Matching for Transmitter ............................................................................ 22
Table-15
Impedance Matching for Receiver ................................................................................ 23
Table-16
Criteria of Starting Speed Adjustment........................................................................... 26
Table-17
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 27
Table-18
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 28
Table-19
AIS Condition ................................................................................................................ 28
Table-20
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 29
Table-21
EXZ Definition ............................................................................................................... 32
Table-22
Interrupt Event............................................................................................................... 35
Table-23
Global Register List and Map........................................................................................ 36
Table-24
Per Channel Register List and Map .............................................................................. 36
Table-25
ID: Device Revision Register ........................................................................................ 37
Table-26
RST: Reset Register ..................................................................................................... 37
Table-27
GCF: Global Configuration Register ............................................................................. 37
Table-28
INTCH: Interrupt Channel Indication Register............................................................... 38
Table-29
TERM: Transmit and Receive Termination Configuration Register .............................. 38
Table-30
JACF: Jitter Attenuation Configuration Register ........................................................... 38
Table-31
TCF0: Transmitter Configuration Register 0 ................................................................. 39
Table-32
TCF1: Transmitter Configuration Register 1 ................................................................. 39
Table-33
TCF2: Transmitter Configuration Register 2 ................................................................. 40
Table-34
TCF3: Transmitter Configuration Register 3 ................................................................. 40
Table-35
TCF4: Transmitter Configuration Register 4 ................................................................. 40
Table-36
RCF0: Receiver Configuration Register 0..................................................................... 41
Table-37
RCF1: Receiver Configuration Register 1..................................................................... 42
Table-38
RCF2: Receiver Configuration Register 2..................................................................... 43
Table-39
MAINT0: Maintenance Function Control Register 0...................................................... 43
Table-40
MAINT1: Maintenance Function Control Register 1...................................................... 44
Table-41
MAINT2: Maintenance Function Control Register 2...................................................... 44
Table-42
MAINT3: Maintenance Function Control Register 3...................................................... 44
Table-43
MAINT4: Maintenance Function Control Register 4...................................................... 45
Table-44
MAINT5: Maintenance Function Control Register 5...................................................... 45
Table-45
MAINT6: Maintenance Function Control Register 6...................................................... 45
Table-46
INTM0: Interrupt Mask Register 0 ................................................................................. 46
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