1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
OCTOBER 2003
2003 Integrated Device Technology, Inc.
DSC - 6395/3
c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five and one bank of
four outputs
Separate output enable for each output bank
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT23S09-1 for Standard Drive
IDT23S09-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Spread spectrum compatible
Available in SOIC and TSSOP packages
IDT23S09
3.3V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
DESCRIPTION:
The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 133MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT23S09 enters power down. In this mode, the device will draw less than
12A for Commercial Temperature range and less than 25A for Industrial
temperature range, and the outputs are tri-stated.
The IDT23S09 is characterized for both Industrial and Commercial
operation.
PLL
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Control
Logic
1
REF
S2
16
CLKOUT
8
9
2
3
14
15
6
7
10
11
FUNCTIONAL BLOCK DIAGRAM
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
PIN CONFIGURATION
SOIC/ TSSOP
TOP VIEW
Symbol
Rating
Max.
Unit
V
DD
Supply Voltage Range
0.5 to +4.6
V
V
I (2)
Input Voltage Range (REF)
0.5 to +5.5
V
V
I
Input Voltage Range
0.5 to
V
(except REF)
V
DD
+0.5
I
IK
(V
I
< 0)
Input Clamp Current
50
mA
I
O
(V
O
= 0 to V
DD
)
Continuous Output Current
50
mA
V
DD
or GND
Continuous Current
100
mA
T
A
= 55C
Maximum Power Dissipation
0.7
W
(in still air)
(3)
T
STG
Storage Temperature Range
65 to +150
C
Operating
Commercial Temperature
0 to +70
C
Temperature
Range
Operating
Industrial Temperature
-40 to +85
C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150C and a board trace length of 750 mils.
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
(1)
Pin Name
Pin Number
Type
Functional Description
REF
(1)
1
IN
Input reference clock, 5 Volt tolerant input
CLKA1
(2)
2
Out
Output clock for bank A
CLKA2
(2)
3
Out
Output clock for bank A
V
DD
4, 13
PWR
3.3V Supply
GND
5, 12
GND
Ground
CLKB1
(2)
6
Out
Output clock for bank B
CLKB2
(2)
7
Out
Output clock for bank B
S2
(3)
8
IN
Select input Bit 2
S1
(3)
9
IN
Select input Bit 1
CLKB3
(2)
10
Out
Output clock for bank B
CLKB4
(2)
11
Out
Output clock for bank B
CLKA3
(2)
14
Out
Output clock for bank A
CLKA4
(2)
15
Out
Output clock for bank A
CLKOUT
(2)
16
Out
Output clock, internal feedback on this pin
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
REF
CLKA1
S2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLKA2
GND
CLKB1
CLKOUT
CLKA4
GND
S1
V
DD
V
DD
CLKB2
CLKB3
CLKB4
CLKA3
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
V
IL
Input LOW Voltage Level
--
0.8
V
V
IH
Input HIGH Voltage Level
2
--
V
I
IL
Input LOW Current
V
IN
= 0V
--
50
A
I
IH
Input HIGH Current
V
IN
= V
DD
--
100
A
V
OL
Output LOW Voltage
Standard Drive
I
OL
= 8mA
--
0.4
V
High Drive
I
OL
= 12mA (-1H)
V
OH
Output HIGH Voltage
Standard Drive
I
OH
= -8mA
2.4
--
V
High Drive
I
OH
= -12mA (-1H)
I
DD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
--
12
A
I
DD
Supply Current
Unloaded Outputs at
66.66MHz, SEL inputs at V
DD
or GND
--
32
mA
SWITCHING CHARACTERISTICS (23S09-1) - COMMERCIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t
1
Output Frequency
10pF Load
10
--
133
MHz
30pF Load
10
--
100
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
= 66.66MHz
40
50
60
%
t
3
Rise Time
Measured between 0.8V and 2V
--
--
2.5
ns
t
4
Fall Time
Measured between 0.8V and 2V
--
--
2.5
ns
t
5
Output to Output Skew
All outputs equally loaded
--
--
250
ps
t
6A
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Measured at V
DD
/2
--
0
350
ps
t
6B
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Measured at V
DD
/2 in PLL bypass mode (IDT23S09 only)
1
5
8.7
ns
t
7
Device-to-Device Skew
Measured at V
DD
/2 on the CLKOUT pins of devices
--
0
700
ps
t
J
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
--
--
200
ps
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
--
--
1
ms
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
Symbol
Parameter
Min.
Max.
Unit
V
DD
Supply Voltage
3
3.6
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
L
Load Capacitance < 100MHz
--
30
pF
Load Capacitance 100MHz - 133MHz
--
10
C
IN
Input Capacitance
--
7
pF
OPERATING CONDITIONS - COMMERCIAL
FUNCTION TABLE
(1)
S2
S1
CLKA
CLKB
CLKOUT
(2)
Output Source
PLL Shut Down
L
L
Tri-State
Tri-State
Driven
PLL
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
Driven
Driven
REF
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
SWITCHING CHARACTERISTICS (23S09-1H) - COMMERCIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t
1
Output Frequency
10pF Load
10
--
133
MHz
30pF Load
10
--
100
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
= 66.66MHz
40
50
60
%
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
<50MHz
45
50
55
%
t
3
Rise Time
Measured between 0.8V and 2V
--
--
1.5
ns
t
4
Fall Time
Measured between 0.8V and 2V
--
--
1.5
ns
t
5
Output to Output Skew
All outputs equally loaded
--
--
250
ps
t
6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2
--
0
350
ps
t
6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2 in PLL bypass mode (IDT23S09 only)
1
5
8.7
ns
t
7
Device-to-Device Skew
Measured at V
DD
/2 on the CLKOUT pins of devices
--
0
700
ps
t
8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
--
--
V/ns
t
J
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
--
--
200
ps
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
--
--
1
ms
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
V
IL
Input LOW Voltage Level
--
0.8
V
V
IH
Input HIGH Voltage Level
2
--
V
I
IL
Input LOW Current
V
IN
= 0V
--
50
A
I
IH
Input HIGH Current
V
IN
= V
DD
--
100
A
V
OL
Output LOW Voltage
Standard Drive
I
OL
= 8mA
--
0.4
V
High Drive
I
OL
= 12mA (-1H)
V
OH
Output HIGH Voltage
Standard Drive
I
OH
= -8mA
2.4
--
V
High Drive
I
OH
= -12mA (-1H)
I
DD_PD
Power Down Current
REF = 0MHz (S2 = S1 = H)
--
25
A
I
DD
Supply Current
Unloaded Outputs at
66.66MHz, SEL inputs at V
DD
or GND
--
35
mA
Symbol
Parameter
Min.
Max.
Unit
V
DD
Supply Voltage
3
3.6
V
T
A
Operating Temperature (Ambient Temperature)
-40
+85
C
C
L
Load Capacitance < 100MHz
--
30
pF
Load Capacitance 100MHz - 133MHz
--
10
C
IN
Input Capacitance
--
7
pF
OPERATING CONDITIONS - INDUSTRIAL
5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
SWITCHING CHARACTERISTICS (23S09-1H) - INDUSTRIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t
1
Output Frequency
10pF Load
10
--
133
MHz
30pF Load
10
--
100
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
= 66.66MHz
40
50
60
%
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
<50MHz
45
50
55
%
t
3
Rise Time
Measured between 0.8V and 2V
--
--
1.5
ns
t
4
Fall Time
Measured between 0.8V and 2V
--
--
1.5
ns
t
5
Output to Output Skew
All outputs equally loaded
--
--
250
ps
t
6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2
--
0
350
ps
t
6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2 in PLL bypass mode (IDT23S09 only)
1
5
8.7
ns
t
7
Device-to-Device Skew
Measured at V
DD
/2 on the CLKOUT pins of devices
--
0
700
ps
t
8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
--
--
V/ns
t
J
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
--
--
200
ps
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
--
--
1
ms
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (23S09-1) - INDUSTRIAL
(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
t
1
Output Frequency
10pF Load
10
--
133
MHz
30pF Load
10
--
100
Duty Cycle = t
2
t
1
Measured at 1.4V, F
OUT
= 66.66MHz
40
50
60
%
t
3
Rise Time
Measured between 0.8V and 2V
--
--
2.5
ns
t
4
Fall Time
Measured between 0.8V and 2V
--
--
2.5
ns
t
5
Output to Output Skew
All outputs equally loaded
--
--
250
ps
t
6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2
--
0
350
ps
t
6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at V
DD
/2 in PLL bypass mode (IDT23S09 only)
1
5
8.7
ns
t
7
Device-to-Device Skew
Measured at V
DD
/2 on the CLKOUT pins of devices
--
0
700
ps
t
J
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
--
--
200
ps
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented on REF pin
--
--
1
ms
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
6
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
Output
1.4V
1.4V
t5
Output
REF
V
DD/
2
t6
Output
CLKOUT
Device 1
t7
CLKOUT
Device 2
V
DD/
2
V
DD
/2
V
DD
/2
1.4V
1.4V
t2
t1
1.4V
2V
0.8V
t3
t4
0.8V
3.3V
0V
2V
Output
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
All Outputs Rise/Fall Time
Input to Output Propagation Delay
Device to Device Skew
Output to Output Skew
Duty Cycle Timing
SWITCHING WAVEFORMS
7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
V
DD
OUTPUTS
CLKOUT
CLOAD
V
DD
GND
GND
0.1
F
0.1
F
V
DD
OUTPUTS
10pF
V
DD
GND
GND
0.1
F
0.1
F
1K
1K
CLKOUT
Test Circuit 1 (all Parameters Except t8)
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
TEST CIRCUITS
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
ORDERING INFORMATION
Ordering Code
Package Type
Operating Range
IDT23S09-1DC
16-Pin SOIC
Commercial
IDT23S09-1DCI
16-Pin SOIC
Industrial
IDT23S09-1HDC
16-Pin SOIC
Commercial
IDT23S09-1HDCI
16-Pin SOIC
Industrial
IDT23S09-1HPG
16-Pin TSSOP
Commercial
IDT23S09-1HPGI
16-Pin TSSOP
Industrial
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
IDT
XXXXX
XX
X
Package
Process
Device Type
Blank
I
23S09-1
23S09-1H
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Zero Delay Clock Buffer with High Drive,
Spread Spectrum Compatible
Small Outline
Thin Shrink Small Outline Package
DC
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