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Электронный компонент: IDT29FCT520BTQ

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INDUSTRIAL TEMPERATURE RANGE
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
1
AUGUST 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4215/5
FEATURES:
A, B, and C grades
Low input and output leakage


1A (max.)
CMOS power levels
True TTL input and output compatibility:
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Available in SOIC, SSOP, and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT29FCT520AT/BT/CT
MULTILEVEL
PIPELINE REGISTER
DESCRIPTION:
The 29FCT520T contains four 8-bit positive edge-triggered registers.
These may be operated as a dual 2-level or as a single 4-level pipeline.
A single 8-bit input is provided and any of the four registers is available at
the 8-bit, 3-state output.
These devices are ideal for high speed burst writes and reads in
processor/memory applications.
M U X
OCTAL REG . B1
OCTAL REG . B2
OCTAL REG. A2
OCTAL REG. A1
M U X
O E
Y
0
- Y
7
8
REG ISTER
C O N TR O L
C LK
I
0
, I
1
1
2
S
0
, S
1
2
D
0
- D
7
8
INDUSTRIAL TEMPERATURE RANGE
2
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
PIN CONFIGURATION
REGISTER SELECTION
S
0
S
1
Register
0
0
B
2
0
1
B
1
1
0
A
2
1
1
A
1
SOIC/ SSOP/ QSOP
TOP VIEW
5
6
7
8
9
10
11
12
G ND
1
2
3
4
24
23
22
21
20
19
18
17
Vcc
16
15
14
13
SO 24-2
SO 24-7
SO 24-8
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
O E
I
0
I
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLK
Y
6
Y
7
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Description
Dx
Register Input Port
CLK
Clock Input. Enter data into registers on LOW-to-HIGH
transitions.
I
0
, I
1
Instruction Inputs. See Figure 1 and INSTRUCTION
CONTROL tables
S
0
, S
1
Multiplexer Select. Inputs one of the following registers to
be available at the Output Port: A
1
, A
2
, B
1
, or B
2.
OE
Output Enable for 3-State Output Port
Y x
Register Output Port
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(4)
V
I
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 8mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 15mA
2
3
--
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 48mA
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 5%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is 5A at T
A
= 55C.
A
1
A
2
B
1
B
2
A
1
A
2
B
1
B
2
I = 2
I = 1
A
1
A
2
B
1
B
2
I = 0
DUAL 2-LEVEL
SINGLE 4-LEVEL
Figure 1. Data Loading in 2-Level Operation
NOTE:
1. I = 3 for hold.
INDUSTRIAL TEMPERATURE RANGE
4
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
= GND
MHz
OE = GND
One Input Togging
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
1.5
3.5
mA
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE = GND
V
IN
= 3.4V
--
2
5.5
One Bit Togging
V
IN
= GND
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
V
IN
= V
CC
--
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE = GND
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
at fi = 2.5MHz
50% Duty Cycle
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + fiNi)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
29FCT520AT
29FCT520BT
29FCT520CT
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PHL
Propagation Delay
C
L
= 50pF
2
14
2
7.5
2
6
ns
t
PLH
CLK to Yx
R
L
= 500
t
PHL
Propagation Delay
C
L
= 50pF
2
13
2
7.5
2
6
ns
t
PLH
S
0
or S
1
to Yx
t
SU
Set-up Time, HIGH or LOW
5
--
2.5
--
2.5
--
ns
Dx to CLK
t
H
Hold Time, HIGH or LOW
2
--
2
--
2
--
ns
Dx to CLK
t
SU
Set-up Time, HIGH or LOW
5
--
4
--
4
--
ns
I
0
or I
1
to CLK
t
H
Hold Time, HIGH or LOW
2
--
2
--
2
--
ns
I
0
or I
1
to CLK
t
PHZ
Output Disable Time
1.5
12
1.5
7
1.5
6
ns
t
PLZ
t
PZH
Output Enable Time
1.5
15
1.5
7.5
1.5
6
ns
t
PZL
t
W
Clock Pulse Width HIGH or LOW
7
--
5.5
--
5.5
--
ns
INDUSTRIAL TEMPERATURE RANGE
6
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
Pulse
G enerator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OU T
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
IN PUT
TIM ING
INPUT
ASYNC HR O NOU S C ON TROL
PRES ET
C LEAR
ETC.
SYN CH RON OUS C ONTR OL
t
S U
t
H
t
RE M
t
S U
t
H
H IGH-LOW -HIG H
PULSE
LOW -H IGH -LOW
PULSE
t
W
1.5V
1.5V
SAM E PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
1.5V
V
O H
t
PL H
O UTPUT
OPPOSITE PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
t
P LH
t
P H L
t
P H L
V
O L
C ONTR OL
INPU T
3V
1.5V
0V
3.5V
0V
OUTPU T
N ORM A LLY
LOW
OUTPU T
N ORM A LLY
H IGH
SW ITCH
CLO SE D
SW ITC H
OPEN
V
O L
0.3V
0.3V
t
PLZ
t
PZL
t
P ZH
t
PH Z
3.5V
0V
1.5V
1.5V
EN AB LE
DISA BLE
V
O H
PRES ET
C LEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
INDUSTRIAL TEMPERATURE RANGE
IDT29FCT520AT/BT/CT
MULTILEVEL PIPELINE REGISTER
7
ORDERING INFORMATION
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
SO
PY
Q
Small Outline IC (SO24-2)
Shrink Sm all Outline Package (SO24-7)
Quarter-size Sm all Outline Package (SO24-8)
520AT
520BT
520CT
M ultilevel Pipeline Register
XXXXX
Device Type
X
Package
IDT29FCT