FEATURES:

· Fast

Detect

Correct

-- IDT49C460E

10ns (max.)

14ns (max.)

-- IDT49C460D

12ns (max.)

18ns (max.)

-- IDT49C460C

16ns (max.)

24ns (max.)

-- IDT49C460B

25ns (max.)

30ns (max.)

-- IDT49C460A

30ns (max.)

36ns (max.)

-- IDT49C460

40ns (max.)

49ns (max.)

· Low-power CMOS

-- Commercial: 95mA (max.)
-- Military: 125mA (max.)

· Improves system memory reliability

-- Corrects all single bit errors, detects all double and some

triple-bit errors

· Cascadable

-- Data words up to 64-bits

· Built-in diagnostics

-- Capable of verifying proper EDC operation via software

control

· Simplified byte operations

-- Fast byte writes possible with separate byte enables

· Functional replacement for 32- and 64-bit configurations of

the AM29C60 and AM29C660

· Available in PGA, PLCC and Fine Pitch Flatpack
· Military product compliant to MIL-STD-883, Class B
· Standard Military Drawing #596288533

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1995

1995 Integrated Device Technology, Inc.

11.6

DSC-9017/8

32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION:

The IDT49C460s are high-speed, low-power, 32-bit Error

Detection and Correction Units which generate check bits on
a 32-bit data field according to a modified Hamming Code and
correct the data word when check bits are supplied. The
IDT49C460s are performance-enhanced functional replace-
ments for 32-bit versions of the 2960. When performing a read
operation from memory, the IDT49C460s will correct 100% of
all single bit errors and will detect all double bit errors and
some triple bit errors.

The IDT49C460s are easily cascadable to 64-bits. Thirty-

two-bit systems use 7 check bits and 64-bit systems use 8
check bits. For both configurations, the error syndrome is
made available.

The IDT49C460s incorporate two built-in diagnostic modes.

Both simplify testing by allowing for diagnostic data to be
entered into the device and to execute system diagnostics
functions.

They are fabricated using a CMOS technology designed for

high-performance and high-reliability. The devices are pack-
aged in a 68-pin ceramic PGA, PLCC and Ceramic Quad
Flatpack.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

DATA

LATCH

ERROR

CORRECT

ERROR

DECODE

MUX

DATA

LATCH

CHECK BIT
GENERATE

MUX

CHECK BIT

IN LATCH

DIAGNOSTIC

LATCH

SYNDROME

GENERATE

ERROR

DETECT

CONTROL

LOGIC

MUX

DATA

031

BYTE

DIAG

OUT

GENERATE

CORRECT

CODE ID

1,0

DIAG MODE

1,0

ERROR
MULT ERROR

2584 drw 01

IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
IDT49C460E

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS

Pin Name

I/O

Description

DATA

031

I/O

32 bidirectional data lines provide input to the Data Input Latch and Diagnostic Latch and also receive output from
the Data Output Latch. DATA

is the LSB; DATA

is the MSB.

Eight check bit input lines input check bits for error detection and also used to input syndrome bits for error
correction in 64-bit applications.

Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input
Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch
follow the input data and input check bits.

OUT

GENERATE

A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the
check bits or GENERATE partial check bits specific to the data in the Data Input Latch. The generated check bits
are placed on the SC outputs. Also, when LOW, the Data Out Latch is latched to its previous state.

When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple
errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch.
In the Correct Mode, single bit errors are also automatically corrected and the corrected data is placed at the
inputs of the Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form
the number of errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the
Data Input Latch as modified by the correction logic network. In Correct Mode, single bit errors are corrected by
the network before being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch
are passed through the correction network unchanged into the Data Output Latch. The Data Output Latch is
disabled, with its contents unchanged, if the EDC is in the Generate Mode.

Syndrome Check Bit outputs. Eight outputs which hold the check bits and partial check bits when the EDC is in
the Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct
modes. All are 3-state outputs.

Output Enable--Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state.
When LOW, all SC output lines are enabled.

ERROR

In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When
HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode.

MULT

ERROR

In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level
indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.

CORRECT

The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input
Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will
drive data directly from the Data Input Latch to the Data Output Latch without correction.

BYTE

Output Enable--Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four
bytes of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH,
they force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is
easily activated by separately selecting the four enable lines.

DIAG
MODE

1,0

Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.

CODE ID

1,0

These two code identification inputs identify the size of the total data word to be processed. The two allowable
data word sizes are 32 and 64 bits and their respective modified Hamming Codes are designated 32/39 and
64/72. Special CODE ID

1,0

, input 01 is also used to instruct the EDC that the signals CODE ID

1,0

, DIAG MODE

1,0

and CORRECT are to be taken from the Diagnostic Latch rather than from the input control lines.

DIAG

This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the
input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic
Latch holds diagnostic check bits and internal control signals for CODE ID

1,0

, DIAG MODE

1,0

and CORRECT.

2584 tbl 01

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

EDC ARCHITECTURE SUMMARY

The IDT49C460s are high-performance cascadable EDCs

used for check bit generation, error detection, error correction
and diagnostics. The function blocks for this 32-bit device
consist of the following:

· Data Input Latch

· Check Bit Input Latch

· Check Bit Generation Logic

· Syndrome Generation Logic

· Error Detection Logic

· Error Correction Logic

· Data Output Latch

· Diagnostic Latch

· Control Logic

DATA INPUT/OUTPUT LATCH

The Latch Enable Input, LE

, controls the loading of 32 bits

of data to the Data In Latch. The data from the DATA lines can
be loaded in the Diagnostic Latch under control of the
Diagnostic Latch Enable, LE

DIAG

, giving check bit information

in one byte and control information in another byte. The
Diagnostic Latch is used in the Internal Control Mode or in one
of the diagnostic modes. The Data Output Latch has buffers
that place data on the DATA lines. These buffers are split into
four 8-bit buffers, each having their own output enable con-
trols. This feature facilitates byte read and byte modify
operations.

CHECK BIT GENERATION LOGIC

This generates the appropriate check bits for the 32 bits of

data in the Data Input Latch. The modified Hamming Code is
the basis for generating the proper check bits.

SYNDROME GENERATION LOGIC

In both the Detect and Correct modes, this logic does a

comparison on the check bits read from memory against the
newly generated set of check bits produced for the data read
in from memory. Matching sets of check bits mean no error
was detected. If there is a mismatch, one or more of the data
or check bits is in error. Syndrome bits are produced by an
exclusive-OR of the two sets of check bits. Identical sets of
check bits mean the syndrome bits will be all zeros. If an error
results, the syndrome bits can be decoded to determine the
number of errors and the specific bit-in-error.

ERROR DETECTION LOGIC

This part of the device decodes the syndrome bits

generated by the Syndrome Generation Logic. With no errors
in either the input data or check bits, both the

ERROR

and

MULTERROR

outputs are HIGH. ERROR will go low if one

error is detected.

MULTERROR

and

ERROR

will both go low

if two or more errors are detected.

ERROR CORRECTION LOGIC

In single error cases, this logic complements (corrects) the

single data bit-in-error. This corrected data is loaded into the
Data Output Latch, which can then be read onto the bidirec-
tional data lines. If the error is resulting from one of the check
bits, the correction logic does not place corrected check bits
on the syndrome/check bit outputs. If the corrected check bits
are needed, the EDC must be switched to the Generate Mode.

DATA OUTPUT LATCH AND OUTPUT BUFFERS

The Data Output Latch is used for storing the result of an

error correction operation. The latch is loaded from the
correction logic under control of the Data Output Latch En-
able, LE

OUT

. The Data Output Latch may also be directly

loaded from the Data Input Latch in the PASSTHRU mode.
The Data Output Latch buffer is split into 4 individual buffers
which can be enabled by

separately for reading onto

the bidirectional data lines.

DIAGNOSTIC LATCH

The diagnostic latch is loadable under control of the

Diagnostic Latch Enable, LE

DIAG

, from the bidirectional data

lines. Check bit information is contained in one byte while the
other byte contains the control information. The Diagnostic
Latch is used for driving the device when in the Internal Control
Mode, or for supplying check bits when in one of the diagnostic
modes.

CONTROL LOGIC

Specifies in which mode the device will be operating in.

Normal operation is when the control logic is driven by external
control inputs. In the Internal Control Mode, the control signals
are read from the Diagnostic Latch. Since LE

OUT

and

GENERATE

are controlled by the same pin, the latching action

(LE

OUT

from high to low) of the Data Output Latch causes the

EDC to go into the Generate Mode.

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED PRODUCT DESCRIPTION

The IDT49C460 EDC units contain the logic necessary to

generate check bits on 32 bits of data input according to a
modified Hamming Code. The EDC can compare internally
generated check bits against those read with the 32-bit data
to allow correction of any single bit data error and detection of
all double (and some triple) bit errors. The IDT49C460s can
be used for 32-bit data words (7 check bits) and 64-bit (8 check
bits) data words.

WORD SIZE SELECTION

The two code identification pins, CODE ID

1, 0

, are used to

determine the data word size that is 32 or 64 bits. They also
select the Internal Control Mode. Table 4 defines all possible
slice identification codes.

CHECK AND SYNDROME BITS

The IDT49C460s provide either check bits or syndrome

bits on the three-state output pins, SC

. Check bits are

generated from a combination of the Data Input bits, while
syndrome bits are an exclusive-OR of the check bits gener-
ated from read data with the read check bits stored with the
data. Syndrome bits can be decoded to determine the single
bit in error or that a double (some triple) error was detected.
The check bits are labeled:

, C

for the 32-bit configuration

, C

for the 64-bit configuration

Syndrome bits are similarly labeled S

through S

2584 tbl 02

Table 2. Diagnostic Mode Control

NOTES:

2584 tbl 03

1. In Generate Mode, data is read into the EDC unit and the check bits are generated. The same data is written to memory along with the check bits. Since

the DATA

OUT

Latch is not used in the Generate Mode, LE

OUT

(being LOW since it is tied to Generate) does not affect the writing of check bits.

2. Error Dep (Error Dependent):

ERROR

will be low for single or multiple errors, with

MULT ERROR

low for double or multiple errors. Both signals are high

for no errors.

3. LE

is LOW.

Table 3. IDT49C460 Operating Modes

Correct

Diag

Mode

Diag

Mode

Diagnostic Mode Selected

Non-diagnostic Mode. Normal
EDC function in this mode.

Diagnostic Generate. The con
tents of the Diagnostic Latch are
substituted for the normally
generated check bits when in the
Generate Mode. The EDC
functions normally in the Detect or
Correct modes.

0/1

Diagnostic Detect/Correct. In
either mode, the contents of the
Diagnostic Latch are substituted
for the check bits normally read
from the Check Bit Input Latch.
The EDC functions normally in the
Generate Mode.

Initialize. The Data Input Latch
outputs are forced to zeros and
latched upon removal of Initialize
Mode.

PASSTHRU.

Operating

Mode

Generate

Correct

DATA

OUT

Latch

07

(

= LOW)

ERROR

MULT ERROR

Generate

0
1

0
0

OUT

= LOW

(1)

Check Bits Generated from

DATA

Latch

High

Detect

0
0

0
1

DATA

Latch

Syndrome Bits DATA

Check Bit Latch

Error Dep

(2)

Correct

0
0

0
1

DATA

Latch w/

Single Bit Correction

Syndrome Bits DATA

Check Bit Latch

Error Dep

PASSTHRU

DATA

Latch

Check Bit Latch

High

Diagnostic
Generate

Check Bits from Diagnostic Latch

High

Diagnostic Detect

DATA

Latch

Syndrome Bits DATA

Diagnostic Latch

Error Dep

Diagnostic Correct

DATA

Latch w/

Single Bit Correction

Syndrome Bits DATA

Diagnostic Latch

Error Dep

Initialization

DATA

Latch

Set to 0000

(3)

Internal

CODE ID

1,0

= 01 (Control Signals CODE ID

1,0

, DIAG MODE

1,0

and CORRECT are taken from Diagnostic Latch.)

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODE SELECTION

Tables 2 and 3 describe the nine operating modes of the

IDT49C460s. The Diagnostic Mode pins -- DIAG MODE

0,1

-- define four basic areas of operation.

GENERATE

and

CORRECT further divide operation into 8 functions, with
CODE ID

1,0

defining the ninth mode as the Internal Mode.

Generate Mode is used to display the check bits on the

outputs SC

. The Diagnostic Generate Mode displays

check bits as stored in the Diagnostic Latch.

Detect Mode provides an indication of errors or multiple

errors on the outputs

ERROR

and

MULT ERROR

. Single bit

errors are not corrected in this mode. The syndrome bits are
provided on the outputs SC

. For the Diagnostic Detect

Mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with

check bits stored in the diagnostic latch rather than with the
check bit latch contents.

Correct Mode is similar to the Detect Mode except that

single bit errors will be complemented (corrected) and made
available as input to the Data Out Latches. Again, the
Diagnostic Correct Mode will correct single bit errors as
determined by syndrome bits generated from the data input
and contents of the diagnostic latches.

The Initialize Mode provides check bits for all zero bit data.

Data Input Latches are set, latched to a logic zero and made
available as input to the Data Out Latches.

The Internal Mode disables the external control pins DIAG

MODE

0,1

and CORRECT to be defined by the Diagnostic

Latch. Even CODE ID

1,0

, although externally set to the 01

code, can be redefined from the Diagnostic Latch data.

Code ID

Slice Selected

32-Bit

Internal Control Mode

64-Bit, Lower 32Bit (031)

64-Bit, Upper 32-Bit (3263)

2584 tbl 04

Table 4. Slice Identification

DATA

031

DATA

031

HIGH

CODE ID

1,0

IDT49C460

0,0

2584 drw 05

Figure 1. 32-Bit Configuration

Figure 2. 64-Bit Configuration

BYTE

DATA

CHECK BITS

2584 drw 07

BYTE

DATA

CHECK BITS

2584 drw 08

Figure 3. 32-Bit Data Format

Figure 4. 64-Bit Data Format

DATA

031

DATA

3263

DATA INPUT

CHECKBIT INPUTS

1/8

IDT74FCT240

DATA

CODE ID

1,0

IDT49C460

(LOWER 32 BITS)

DATA

CODE ID

1,0

IDT49C460

(UPPER 32 BITS)

ERROR

MULT

ERROR

MULT

ERROR

SYNDROME/

CHECK BITS

1,1

1,0

2584 drw 06

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT DATA WORD CONFIGURATION

A single IDT49C460 EDC unit, connected as shown in

Figure 1, provides all the logic needed for single bit error
correction and double bit error detection of a 32-bit data field.
The identification code indicates 7 check bits are required.
The CB

pin should be HIGH.

Figure 3 indicates the 39-bit data format for two bytes of

data and 7 check bits. Table 3 describes the operating mode
available.

Table 6 indicates the data bits participating in the check bit

generation. For example, check bit C

is the exclusive-OR

function of the 16 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits from the respective latch are passed,
unchanged, in the PASSTHRU or Diagnostic Generate Mode.

Syndrome bits are generated by an exclusive-OR or the

generated check bits with the read check bits. For example,
S

is the XOR of check bits C

from those read with those

generated. Table 7 indicates the decoding of the seven
syndrome bits to identify the bit-in-error for a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.

In the Correct Mode, the syndrome bits are used to

complement (correct) single bit errors in the data bits. For
double or multiple error detection, the data available as input
to the Data Out Latch is not defined.

Table 5 defines the bit definition for the Diagnostic Latch.

As defined in Table 3, several modes will use the diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SC

outputs. The Internal Mode substitutes the

indicated bit position for the external control signals.

2584 drw 05

Table 5. 32-Bit Diagnostic Latch Coding Format

BIT 0

DIAGNOSTIC

BIT 1

DIAGNOSTIC

BIT 2

DIAGNOSTIC

BIT 3

DIAGNOSTIC

BIT 4

DIAGNOSTIC

BIT 5

DIAGNOSTIC

BIT 6

DIAGNOSTIC

BIT 7

DIAGNOSTIC

BIT 8

CODE ID

BIT 9

CODE ID

BIT 10

DIAG MODE

BIT 11

DIAG MODE

BIT 12

CORRECT

BIT 1331

DON'T CARE

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

2584 tbl 06

Table 6. 32Bit Modified Hamming CodeCheck Bit Encode Chart

2584 tbl 07

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Table 3 describes the operating modes available for the 64/

72 configuration.

Table 11 indicates the data bits participating in the check bit

generation. For example, check bit C

is the exclusive-OR

function of the 32 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
modes. Check bits are passed as stored in the PASSTHRU or
Diagnostic Generate modes.

Syndrome bits are generated by an exclusive-OR of the

generated check bits with the read check bits. For example,
S

is the XOR of check bits C

from those read with those

generated. Table 9 indicates the decoding of the 8 syndrome
bits to determine the bit in error for a single bit error or whether
a double or triple bit error was detected. The all zero case
indicates no errors detected.

In the Correct Mode, the syndrome bits are used to

complement (correct) single bit errors in the data bits. For
double or multiple error detection, the data available as input
to the Data Out Latch is not defined.

Tables 8A and 8B define the bit definition for the Diagnostic

Latch. As defined in Table 3, several modes will use the
Diagnostic Check Bits to determine syndrome bits or to pass
as check bits to the SC

outputs. The Internal Mode sub-

stitutes the indicated bit position for the external control
signals.

Performance data is provided in Table 10, relating a single

IDT49C460 EDC with the two cascaded units of Figure 2. As
indicated, a summation of propagation delays is required from
the cascading arrangement of EDC units.

NOTES:

2584 tbl 08

1. * = No errors detected
2. Number = The number of the single bit-in-error
3. T = Two errors detected
4. M = Three or more errors detected

Table 7. Syndrome Decode to Bit-in-Error (32-Bit)

64-BIT DATA WORD CONFIGURATION

Two IDT49C460 EDC units, connected as shown in Figure

2, provide all the logic needed for single bit error detection and
double bit error detection of a 64-bit data field. Table 4 gives
the CODE ID

1,0

values needed for distinguishing the upper 32

bits from the lower 32 bits. Valid syndrome, check bits and the

ERROR

and

MULT ERROR

signals come from the IC with the

CODE ID

1,0

= 11. Control signals not indicated are connected

to both units in parallel. The EDC with the CODE ID

1,0

= 10

has the

grounded. The

selects the syndrome bits

from the EDC with CODE ID

1,0

= 11 and also controls the

check bit buffers from memory.

Data In bits 0 through 31 are connected to the same

numbered inputs of the EDC unit with CODE ID

1,0

= 10, while

Data In bits 32 through 63 are connected to Data Inputs 0 to
31, respectively, for the EDC unit with CODE ID

1,0

= 11.

Figure 4 indicates the 72-bit data format of 8 bytes of data

and 8 check bits. Check bits are input to the EDC unit with
CODE ID

1,0

= 10 through a three-state buffer unit such as the

IDT74FCT244. Correction of single bit errors of the 64-bit
configuration requires a feedback of syndrome bits from the
upper EDC unit to the lower EDC unit. The MUX shown on the
functional block diagram is used to select the CB

pins as

the syndrome bits rather than internally generated syndrome
bits.

2584 tbl 09

Table 8A. 64-Bit Diagnostic LatchCoding Format

(Diagnostic and Correct Mode)

Bit

Internal Function

DIAGNOSTIC

CODE ID

LOWER 32-BIT

CODE ID

LOWER 32-BIT

DIAG MODE

LOWER 32-BIT

DIAG MODE

LOWER 32-BIT

CORRECT LOWER 32-BIT

1331

DON'T CARE

3239

DON'T CARE

CODE ID

UPPER 32-BIT

CODE ID

UPPER 32-BIT

DIAG MODE

UPPER 32-BIT

DIAG MODE

UPPER 32-BIT

CORRECT UPPER 32-BIT

4563

DON'T CARE

Hex

Syndrome

Bits

Hex S

C4 C5

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Bit

Internal Function

DON'T CARE

CODE ID

LOWER 32-BIT

CODE ID

LOWER 32-BIT

DIAG MODE

LOWER 32-BIT

DIAG MODE

LOWER 32-BIT

CORRECT LOWER 32-BIT

1331

DON'T CARE

DIAGNOSTIC

CODE ID

UPPER 32-BIT

CODE ID

UPPER 32-BIT

DIAG MODE

UPPER 32-BIT

DIAG MODE

UPPER 32-BIT

CORRECT UPPER 32-BIT

4563

DON'T CARE

2584 tbl 10

Table 8B. 64-Bit Diagnostic LatchCoding Format (Diagnostic and Correct Mode)

Hex

Syndrome

Bits

Hex

NOTES:

2584 tbl 11

* = No errors detected

T = Two errors detected

Number = The number of the single bit-in-error

M = Three or more errors detected

Table 9. Syndrome Decode to BitInError (64Bit Configuration)

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

2584 tbl 13

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

2584 tbl 14

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

2584 tbl 15

Generated

Participating Data Bits

Check Bits

Parity

Even (XOR)

Odd (XNOR)

Even (XOR)

NOTE:

2584 tbl 16

1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table.

Table 11. 64Bit Modified Hamming CodeCheck Bit Encoding

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SC OUTPUTS

The tables below indicate how the SC

outputs are

generated in each control mode of various CODE IDs (Internal
Control Mode not applicable).

Correct/

CODE ID

1,0

Detect

PH0

PH1

PH2

Final

Syndrome

Partial

Syndrome

Final

Syndrome

2584 tbl 17

2584 tbl 19

CODE ID

1,0

Generate

PH0

PH1

PH2

Final

Check Bits

Partial

Check Bits

Final

Check Bits

Diagnostic

Correct/

CODE ID

1,0

Detect

PH0

DL0

PH1

DL0

PH2

DL1

DL2

DL3

DL4

DL5

DL6

DL7

Final

Syndrome

Partial

Syndrome

Final

Syndrome

Diagnostic

CODE ID

1,0

Generate

DL0

DL32

DL1

DL33

DL2

DL34

DL3

DL35

DL4

DL36

DL5

DL37

DL6

DL38

DL7

DL39

Final

Check Bits

Partial

Check Bits

Final

Check Bits

2584 tbl 20

2584 tbl 18

CODE ID

1,0

PASSTHRU

2584 tbl 21

Table 12. SC0-7 Outputs For Different Control Modes

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL EQUATIONS

The equations below describe the IDT49C460 output val-

ues as defined by the value of the inputs and internal states.

DEFINITIONS

PA = D

= D

PD = D

PE = D

PF = D

PG = D

PH0 = D

PH1 = D

PH2 = D

DATA CORRECTION

The tables below indicate which data output bits are

corrected depending upon the syndromes and the CODE
ID

1,0

position. The syndromes that determine data correction

are, in some cases, syndromes input externally via the CB
inputs and, in some cases, syndromes input externally by that
EDC (S

are the internal syndromes and are the same as the

value of the SC

output of that EDC if enabled).

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

CAPACITANCE

= + 25

C, f = 1.0MHz)

Symbol

Rating

Com'l.

Mil.

Unit

TERM

Terminal Voltage
with Respect to
GND

0.5 to

+ 0.5V

0.5 to

+ 0.5V

Power Supply
Voltage

-0.5 to +7.0

Operating
Temperature

0 to +70

55 to +125

BIAS

Temperature
Under Bias

55 to +125

65 to +135

STG

Storage
Temperature

55 to +125

65 to +150

OUT

DC Output Current

Symbol

Parameter

(1)

Conditions

Typ.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

NOTE:

2584 tbl 25

1. This parameter is sampled and not 100% tested.

NOTE:

2584 tbl 24

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: V

= 0.2V; V

= V

0.2V

Commercial: T

= 0

C to +70

C, V

= 5.0V

5%; Military: T

= 55

C to +125

C, V

= 5.0V

10%

NOTES:

2584 tbl 26

1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V

= 5.0V, + 25

C ambient and maximum loading.

3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

Symbol

Parameter

Test Conditions

(1)

Min.

Typ.

(2)

Max.

Unit

Input HIGH Level

Guaranteed Logic HIGH Level

(4)

2.0

Input LOW Level

Guaranteed Logic LOW Level

(4)

0.8

I H

Input HIGH Current

= Max., V

= V

0.1

10.0

I L

Input LOW Current

= Max., V

= GND

0.1

10.0

Output HIGH Voltage

= Min.

= 300

= 12mA Mil.

2.4

4.3

= 15mA Com'l.

2.4

4.3

Output LOW Voltage

= Min.

= 300

GND

= 12mA Mil.

0.3

0.5

= 16mA Com'l.

0.3

0.5

Off State (High Impedance)

= Max.

= 0V

0.1

20.0

Output Current

= V

(Max.)

0.1

20.0

Output Short Circuit Current

= Max., V

OUT

= 0V

(3)

30.0

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd.)

Commercial: T

= 0

C to +70

C, V

= 5.0V

5%; Military: T

= 55

C to +125

C, V

= 5.0V

10%

= 0.2V; V

= V

0.2V

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

CCQ

Quiescent Power Supply Current

= Max.; All Inputs

3.0

(CMOS Inputs)

, V

= 0; Outputs Disabled

CCT

Quiescent Input Power Supply

= Max., V

= 3.4V, f

= 0

0.3

0.75

mA/

Current (per Input @ TTL High)

(5)

Input

CCD

Dynamic Power Supply Current

= Max.

MIL.

mA/

, V

COM'L.

MHz

Outputs Open,

= L

Total Power Supply Current

(6)

= Max., f

= 10MHz

MIL.

110

Outputs Open,

= L

COM'L.

50 % Duty cycle

, V

= Max., f

= 10MHz

MIL.

125

Outputs Open,

= L

COM'L.

50 % Duty cycle

= 3.4V, V

= 0.4V

NOTES:

2584 tbl 27

5. I

CCT

is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out I

CCQ

, then dividing by the total number of inputs.

6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply

Current can be calculated by using the following equation:
I

= I

CCQ

+ I

CCT

x D

) + I

CCD

)

= Data duty cycle TTL high period (V

= 3.4V).

= Number of dynamic inputs driven at TTL levels.

= Operating frequency in Megahertz.

CMOS TESTING CONSIDERATIONS

Special test board considerations must be taken into

account when applying high-speed CMOS products to the
automatic test environment. Large output currents are being
switched in very short periods and proper testing demands
that test set-ups have minimized inductance and guaranteed
zero voltage grounds. The techniques listed below will assist
the user in obtaining accurate testing results:

1) All input pins should be connected to a voltage potential

during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.

2) Placement and value of decoupling capacitors is critical.

Each physical set-up has different electrical
characteristics and it is recommended that various
decoupling capacitor sizes be experimented with.
Capacitors should be positioned using the minimum lead
lengths. They should also be distributed to decouple
power supply lines and be placed as close as possible to
the DUT power pins.

3) Device grounding is extremely critical for proper device

testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to the DUT interface board and wiring
unused interconnect pins to the ground plane is
recommended. Heavy gauge stranded wire should be
used for power wiring, with twisted pairs being
recommended for minimized inductance.

4) To guarantee data sheet compliance, the input thresholds

should be tested per input pin in a static environment. To
allow for testing and hardware-induced noise, IDT
recommends using V

0V and V

3V for AC tests.

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRELIM

INARY

NOTE: (15) above applies to correction path.

2584 tbl 71

IDT49C460E AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to +70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

NOTES:

2584 tbl 73

1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.

OUTPUT ENABLE/DISABLE TIMES

(5)

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

2584 tbl 70

2584 tbl 72

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

(Internal Control Mode) From

latched to Transparent

(6)

Mode

DATA

031

(Internal Control Mode)

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

(4)

DATA

031(4, 6)

OUT

GENERATE

(15)

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 30

NOTE: (15) above applies to correction path.

2584 tbl 29

IDT49C460D AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to +70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 28

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

NOTES:

2584 tbl 31

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

OUTPUT ENABLE/DISABLE TIMES

(5)

(6)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

(Internal Control Mode) From

latched to Transparent

(6)

Mode

DATA

031

(Internal Control Mode)

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

(4)

DATA

031(4, 6)

OUT

GENERATE

(15)

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OUTPUT ENABLE/DISABLE TIMES

(5)

IDT49C460D AC ELECTRICAL CHARACTERISTICS

(Guaranteed Military Range Performance) Temperature range: 55

C to +125

C, V

= 5.0V

10%

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 32

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

NOTES:

2584 tbl 35

1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F.
6. Not production tested, guaranteed by characterization.

NOTE: (15) above applies to correction path.

2584 tbl 33

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 34

(6)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

03(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

From latched to Transparent

(6)

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(15)

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460C AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to +70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 36

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 39

NOTE: (16) above applies to correction path.

2584 tbl 37

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 38

(6)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

(2)

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

From latched to Transparent

(6)

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(16)

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460C AC ELECTRICAL CHARACTERISTICS

(Guaranteed Military Range Performance) Temperature range: 55

C to +125

C, V

= 5.0V

10%

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 40

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 43

1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F.
6. Not production tested, guaranteed by characterization.

Note: (19) above applies to correction path.

2584 tbl 41

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 42

(6)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

From latched to Transparent

(6)

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(19)

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460B AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to +70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 44

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

2584 tbl 45

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 47

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 46

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

(6)

From latched to Transparent

(2)

DIAG

From latched to Transparent

(6)

Internal

Control

DIAG

From latched to Transparent

(6)

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2584 tbl 48

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

2584 tbl 49

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 51

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 50

IDT49C460B AC ELECTRICAL CHARACTERISTICS

(Guaranteed Military Range Performance) Temperature range: 55

C to +125

C, V

= 5.0V

10%

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

From latched to Transparent

DIAG

From latched to Transparent

Internal

Control

DIAG

From latched to Transparent

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2584 tbl 52

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

2584 tbl 53

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 55

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

2584 tbl 54

IDT49C460A AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to 70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

From latched to Transparent

DIAG

From latched to Transparent

Internal

Control

DIAG

From latched to Transparent

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460A AC ELECTRICAL CHARACTERISTICS

(Guaranteed Military Range Performance) Temperature range: 55

C to +125

C, V

= 5.0V

10%

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 56

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

2584 tbl 57

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

OUTPUT ENABLE/DISABLE TIMES

(5)

2584 tbl 58

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

NOTES:

2584 tbl 59

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

From latched to Transparent

DIAG

From latched to Transparent

Internal

Control

DIAG

From latched to Transparent

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

03(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460 AC ELECTRICAL CHARACTERISTICS

(Guaranteed Commercial Range Performance) Temperature range: 0

C to +70

C, V

= 5.0V

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

2584 tbl 60

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

OUTPUT ENABLE/DISABLE TIMES

(5)

NOTES:

2584 tbl 63

2584 tbl 61

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

From latched to Transparent

DIAG

From latched to Transparent

Internal

Control

DIAG

From latched to Transparent

Mode

DATA

031

Via Diagnostic Latch

(2)

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

(4, 6)

OUT

GENERATE

DATA

031

(4, 6)

DIAG

2584 tbl 62

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C460 AC ELECTRICAL CHARACTERISTICS

(Guaranteed Military Range Performance) Temperature range: 55

C to +125

C, V

= 5.0V

10%

The inputs switch between 0V to 3V with signal measured at the 1.5V level.

PROPAGATION DELAYS

(1)

OUTPUT ENABLE/DISABLE TIMES

(5)

Enable

Disable

From Input

Enable

Disable

To Output

Min.

Max.

Min.

Max.

Unit

OE Byte

DATA

031

2584 tbl 64

SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES

2584 tbl 65

MINIMUM PULSE WIDTHS

Min.

, LE

OUT

GENERATE

, LE

DIAG

(Positivegoing pulse)

NOTES:

2584 tbl 67

1. CI = 5pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.

To Output

From Input

07

DATA

031

ERROR

MULT ERROR

Unit

DATA

031(3)

(2)

(CODE ID

1,0

= 00, 11)

(CODE ID

1,0

= 10)

OUT

GENERATE

CORRECT
Not Internal Control Mode

DIAG MODE
Not Internal Control Mode

CODE ID

1,0

From latched to Transparent

DIAG

From latched to Transparent

Internal

Control

DIAG

From latched to Transparent

(2)

Mode

DATA

031

Via Diagnostic Latch

From Input

To Input

(Latching Data)

Set-up Time

Min.

Hold Time

Min.

Unit

DATA

031(4)

07(4)

DATA

031(4, 6)

OUT

GENERATE

(CODE ID 00, 11)

(4, 6)

OUT

GENERATE

(CODE ID 10)

(4, 6)

OUT

GENERATE

CORRECT

(4, 6)

OUT

GENERATE

DIAG MODE

(4, 6)

OUT

GENERATE

CODE ID

1,0(4, 6)

OUT

GENERATE

IN(4, 6)

OUT

GENERATE

DATA

031(4, 6)

DIAG

2584 tbl 66

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETECT OR CORRECTION MODE (FROM GENERATE MODE)

NOTES:

2584 drw 10

1. BOLD indicates critical parameters.
2. This is "E" version timing spec. Check appropriate table for other speed versions.
* Assumes "CB

" and/or "DATA

" are valid at least 4ns before "LE

" goes high.

CORRECT

DATA bus

OE byte

= High to DATA

OUT

Disabled

OE byte

= High to DATA

OUT

Disabled

OE byte

= Low to DATA

OUT

Enabled

OE byte

= Low to DATA

OUT

Enabled

DATA

to DATA

OUT

Max.
Max.
Max.

Min.
Max.
Min.
Max.

Max.

Propagation Delay

From

Min./Max.

= High to SC

OUT

Disabled

= High to SC

OUT

Disabled

= Low to SC

OUT

Enabled

= Low to SC

OUT

Enabled

OUT

(Syndrome Bits Come Out)

Min.
Max.
Min.
Max.

(Corrected DATA if Correct Mode)
(DATA

if Detect Mode)

CORRECT = High to DATA

OUT

to DATA

OUT

to DATA

OUT

*LE

= High to DATA

OUT

GEN

= High to DATA

OUT

GEN

= High to

MERROR

= Low

OUT

GEN

= High to

ERROR

= Low

DATA

ERROR

= Low

ERROR

= Low

*LE

= High to

ERROR

= Low*

(Low = Error)
DATA

MERROR

= Low

MERROR

= Low

*LE

= High to

MERROR

= Low*

(Low = Error)
DATA

to SC

OUT

to SC

OUT

Max.

Max.
Max.
Max.

Max.
Max.
Max.
Max.
Max.
Max.

Max.
Max.

OUT

GEN

ERROR

MERROR

Valid DATA

Valid Checkbits In

OUT

(Output)

Valid

16*

13*

19*

CODE ID1,0 = 00, 11

CODE ID1,0 = 00, 11
CODE ID1,0 = 10

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERATE MODE (FROM DETECT OR CORRECTION MODE)

NOTES:
1. BOLD indicates critical parameters.
2. Valiid "DATA" and valid CB

" are shown to occur simultaneously, since both buses are latched and opened by the "LE

" input.

3. This is "E" version timing spec. Check appropriate table for other speed versions.
* Assumes DATA bus becomes input 4ns before LE

goes high.

= High to SC

OUT

Disabled

= High to SC

OUT

Disabled

= Low to SC

OUT

Enabled

= Low to SC

OUT

Enabled

CORRECT

OUT

ERR/MERR

OUT

GEN

DATA Bus

OE byte

= High to DATA

OUT

Disabled

OE byte

= High to DATA

OUT

Disabled

OE byte

= Low to DATA

OUT

Enabled

OE byte

= Low to DATA

OUT

Enabled

to DATA

OUT

GENERATE

= Low to

ERROR

= High

OUT

GENERATE

= Low to SC

OUT

DATA

to SC

OUT

*LE

= High to SC

OUT

to SC

OUT

(Forced High)

(Check Bits Exit)

(Don't Care)

Min.
Max.
Min.
Max.

Max.

Max.
Max.
Max.
Max.

Propagation Delay

From

Min./Max.

2584 drw 09

16*

Valid Checkbits In

CODE ID 1,0 = 10

(Generate Mode)

(CODE ID 1,0 = 10)

Valid Checkbits

Valid DATA

OUT

(Output)

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP AND HOLD TIMES AND MINIMUM PULSE WIDTHS

NOTES:

2584 drw 11

1. BOLD indicates critical parameters.
2. This is "E" version timing spec. Check appropriate table for other speed versions.
*

Enable to enable timing requirement to ensure that the last DATA word applied to "DATA

" is made available as DATA

OUT

"; assumes that "DATA

is valid at least 4ns before "LE

" goes high.

CORRECT

DATA

Set-up to LE

= Low

Hold to LE

= Low

Min.
Min.

Set-up/Hold Time

With Respect To

Min./Max.

*LE

= High to LE

OUT

GEN

= Low*

DATA Set-up to LE

= Low

DATA Hold to LE

= Low

Set-up to LE

OUT

GEN

= Low

Set-up to LE

OUT

GEN

= Low

DATA Set-up to LE

OUT

GEN

= Low

Min.

OUT

GEN

width

OUT

GENERATE

Width

CORRECT Set-up to
LE

OUT

GEN

= Low

Min.

Min.
Min.
Min.

Valid

CODE ID1,0 = 00, 11
CODE ID1,0 = 10

14*

6
6

Valid

OUTPUTS

2584 drw 13

2584 drw 12

Figure 5. Input Structure (All Inputs)

Figure 6. Out put Structure

ESD

PROTECTION

INPUTS

INPUT/OUTPUT INTERFACE CIRCUIT

11.6

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST LOAD CIRCUIT

2584 drw 14

DEFINITIONS:
C

= Load capacitance: includes jig and probe capacitance

= Termination resistance: should be equal to Z

OUT

of the Pulse Generator

Figure 7.

VOUT

50pF

500

+ 7.0V

500

D.U.T.

VCC

VIN

Pulse

Generator

ORDERING INFORMATION

IDT

49C460

Device Type

Speed

Package

Process/

Temperature

Range

BLANK
B

G
J
FF

Blank
A
B
C
D
E

Commercial (0

C to + 70

Military ( 55

C to + 125

Compliant to MIL-STD-883, Class B

Pin Grid Array
Plastic Leaded Chip Carrier
Fine Pitch Flatpack

Standard Speed
High-Speed
Very High-Speed
Super-High-Speed
Ultra-High Speed
Fastest Speed

49C460

32-Bit E. D. C.

2584 drw 15

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

1V/ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 7

2584 tbl 69

Test

Switch

Disable Low

Closed

Enable Low

All other Tests

Open

2584 tbl 68

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT49C460CGB

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT49C460CGB