Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc.
11.7
DSC-9028/7
32-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
IDT49C465
IDT49C465A
The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.
FEATURES
32-bit wide Flow-thruEDC
TM
unit, cascadable to 64 bits
Single-chip 64-bit Generate Mode
Separate system and memory buses
On-chip pipeline latch with external control
Supports bidirectional and common I/O memories
Corrects all single-bit errors
Detects all double-bit errors, some multiple-bit errors
Error Detection Time -- 12ns
Error Correction Time -- 14ns
On chip diagnostic registers.
Parity generation and checking on system data bus
Low power CMOS -- 100mA typical at 20MH
Z
144-pin PGA and PQFP packages
Military product compliant to MIL-STD 883, Class B
DESCRIPTION
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC
unit. The chip provides single-error correction and two and
three bit error detection of both hard and soft memory errors.
It can be expanded to 64-bit widths by cascading 2 units,
without the need for additional external logic. The Flow-
thruEDC has been optimized for speed and simplicity of
control.
The EDC unit has been designed to be used in either of two
configurations in an error correcting memory system. The
bidirectional configuration is most appropriate for systems
using bidirectional memory buses. A second system
configuration utilizes external octal buffers, and is well suited
for systems using memory with separate I/O buses.
The IDT49C465/A supports partial word writes, pipelining
and error diagnostics. It also provides parity protection for
data on the system side.
2552 drw 01
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
MD
Latch
Memory
Checkbit
Generator
Checkbit
Latch
Mux
Byte
Mux
System
Checkbit
Generator
Mux
Detect
Logic
Correct
Logic
Expansion
Logic
Syndrome
Generator
SD
Latch
Pipeline
Latch
MD
031
MLE
CBI
07
PCBI
07
SD
031
SLE
PLE
CONTROL
CONTROL
CONTROL
CONTROL
CBO
07
MERR
ERR
1
11.7
2
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
PQFP
TOP VIEW
2552 drw 02
49C465Y
PQ144-2
1
144
109
108
73
72
37
36
V
CC
MD
30
MD
29
MD
28
MD
27
MD
26
MD
25
MD
24
GND
MD
23
MD
22
MD
21
MD
20
MD
19
MD
18
MD
17
MD
16
GND
MOE
MLE
MD
15
MD
14
MD
13
MD
12
MD
11
MD
10
GND
MD
9
MD
8
MD
7
MD
6
MD
5
MD
4
MD
3
V
CC
V
CC
V
CC
SD
5
SD
6
SD
7
SD
8
SD
9
SD
10
SD
11
GND
BE
1
SD
12
SD
13
SD
14
SD
15
SLE
PLE
SOE
GND
SD
16
SD
17
SD
18
SD
19
BE
2
SD
20
SD
21
SD
22
GND
SD
23
SD
24
SD
25
SD
26
SD
27
BE
3
SD
28
V
CC
V
CC
SD
4
BE
0
SD3
SD
2
SD
1
SD
0
PCBI
7
PCBI
6
PCBI
5
PCBI
4
PCBI
3
PCBI
2
PCBI
1
PCBI
0
CODE ID
1
CODE ID
0
GND
GND
MODE
1
MODE
0
MERR
ERR
SYO
7
SYO
6
SY0
5
SY0
4
GND
SY0
3
SYO
2
SYO
1
SYO
0
MD
0
MD
1
MD
2
V
CC
V
CC
VCC
MD
31
CBI
7
CBI
6
CBI
5
CBI
4
GND
CBI
3
CBI
2
CBI
1
CBI
0
CLEAR
SCLKEN
SYNCLK
MODE 2
P
0
P
1
GND
GND
P
2
P
3
PERR
PSEL
CBO
7
CBO
6
CBO
5
CBO
4
CBOE
CBO
3
CBO
2
CBO
1
CBO
0
SD
31
SD
30
SD
29
V
CC
11.7
3
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
2552 drw 03
PGA (CAVITY UP)
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
11
10
9
8
7
6
5
4
3
2
1
15
14
13
12
V
CC
SD
2
SD
6
SD
4
SD
5
SD
7
SD
10
SD
12
SD
11
SD
9
SD
15
SD
13
SD
19
SD
17
SD
18
SD
20
SD
25
SD
22
SD
21
SD
28
SD
26
SD
23
SD
27
SD
29
SD
14
SD
16
PCBI
6
PCBI
5
PCBI
4
PCBI
7
BE
0
SD
3
SD 0
PCBI
3
PCBI
1
V
CC
SD
8
BE
1
GND
SLE
SOE
PLE
GND
BE
2
GND SD
24
BE
3
V
CC
V
CC
V
CC
SD
30
SD
31
CB0
1
CB0
3
CB0
2
CB0
5
CB0
0
CBOE
CB0
4
CB0
7
CB0
6
PERR
PSEL
GND
P
3
P
2
GND
MODE
2
P
1
SCLK
EN
SYN-
CLK
P
0
GND
CB1
0
CB1
6
CB1
3
CB1
1
CB1
7
CB1
4
CB1
2
CLEAR
CB1
5
V
CC
MD
31
MD
30
MD
29
MD
26
MD
24
MD
22
MD
19
MD
18
MD
16
MD
17
MD
28
MD
25
MD
23
MD
21
V
CC
MD
27
GND
MD
20
GND
MD
14
MOE
MLE
MD
15
MD
13
MD
12
MD
11
MD
10
MD
7
MD
4
MD
8
GND
MD
9
MD
6
MD
3
V
CC
V
CC
GND
GND
GND
CODE
ID
1
CODE
ID
0
PCBI
0
SD
1
PCBI
2
MODE
1
MERR ERR
MODE
0
MD
1
MD
5
MD
2
V
CC
SYO
7
SYO
6
SYO
4
SYO
5
SYO
2
SYO
0
SYO
3
MD
0
SYO
1
G144-2
NC*
*Tied to Vcc internally
11.7
4
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2552 drw 04
DETAILED FUNCTIONAL BLOCK DIAGRAM
MUX
ERROR
DETECT
PIPE
LATCH
SD
LATCH
PARITY
GEN
PARITY
CHECK
CONTROL
LOGIC
MUX
MUX
MUX
INTERNAL
FINAL
SYNDRO
ME
SYNDROME
GENERATOR
MUX
ERROR DATA LATCH
DIAGNOSTIC
LATCHES
BYTE MUX
CLEAR
INTERNAL SYNCLK
MD
CHECKBIT
GENERATOR
MUX
CHECK
BIT
LATCH
MUX
MD
LATCH
SD
CHECKBIT
GENERATOR
SD
CHECKBIT
GENERATOR
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
2
3
ERR
MERR
SYO
07
PLE
SOE
BE
03
SD
031
SLE
PSEL
P
03
PERR
SYNCLK
SCLKEN
CLEAR
MODE
02
CODE ID
0,1
PCBI
07
CBOE
CBO
07
MOE
MD
031
CBI
07
MLE
PCBI
07
BE
03
INTERNAL SYNCLK
/ERR
Dashed Line = Diagnostic path
ERROR
CORRECT
1 OF 4
BYTES
11.7
5
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various
configurations in an EDC system. The basic configurations
are shown below.
Figure 1 illustrates a bidirectional configuration, which is
most appropriate for systems using bidirectional memory
buses. It is the simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.
Figure 1. Common I/O Configuration
Figure 2 illustrates a separate I/O configuration. This is
appropriate for systems using separate I/O memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SD outputs
for the system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.
Figure 3 illustrates a third configuration which utilizes
external buffers and is also well suited for systems using
memory with separate I/O buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in "bus-watch" mode. As in the
separate I/O configuration, corrected data is output on the SD
outputs.
Figure 4 illustrates the single-chip generate-only mode for
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straight-
forward, fast and requires no extra hardware for the
expansion.
Figure 2. Separate I/O Configuration
Figure 3. Bypassed Separate I/O Configuration
Figure 4. Separate Generate/Correction Units
with 64-Bit Checkbit Generation
BUFFER
MEMORY
OUTPUT BUS
MEMORY
INPUT BUS
MEMORY
INPUT BUS
CHECK
BITS OUT
CHECK
BITS IN
CBO
64-BIT
GEN.
ONLY
EDC
BUFFER
BUFFER
BUFFER
CBI
LOWER
DATA
UPPER
DATA
EDC
EDC
CPU BUS
2552 drw 08
CPU
I/O
MEMORY
I/O
CHECKBITS
SD
MD
CBI
CBO
EDC
2552 drw 05
EXT.BUFFER
MEMORY
INPUT BUS
CHECKBIT
I/O
MEMORY
OUTPUT BUS
EXT. BUFFER
EXT. BUFFER
CPU BUS
EDC
SD
MD
CBI
CBO
2552 drw 07
CPU
MEMORY
INPUTS
MEMORY
OUTPUTS
CHECKBITS
CBO
CBI
MD
SD
EDC
EXT. BUFFER
2552 drw 06
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