Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
11.7
DSC-2617/9
64-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc.
FEATURES:
64-bit wide Flow-thruEDC
TM
Separate System and Memory Data Input/Output Buses
-- Error Detect Time: 10ns
-- Error Correct Time: 15ns
Corrects all single bit errors; Detects all double bit errors
and some multiple bit errors
Configurable 16-deep bus read/write FIFOs with flags
Simultaneous check bit generation and correction of memory
data
Supports partial word writes on byte boundaries
Low noise output
Sophisticated error diagnostics and error logging
Parity generation on system data bus
208-pin Plastic Quad Flatpack
2617 drw 01
SD
CHK-BIT
LATCH
WRITE
BUFFER
16 WORDS BY
72
SD
LATCH
IN
MD
LATCH
OUT
READ BUFFER
16 WORDS BY
64
MD
LATCH
IN
SD
LATCH
OUT
ERROR
CORRECT
CHECK-BIT
COMPARATOR &
SYNDROME
GENERATOR &
ERROR
DETECTOR
SD
CHECK-BIT
GENERATOR
MD
CHECK-BIT
GENERATOR
B
Y
T
E
M
U
X
MD
CHK-BIT
LATCH
WRITE BACK PATH
DIAGNOSTIC
& STATUS
REGISTERS
PARITY
GENERATE &
PARITY CHECK
PARITY
SD0-63
ERR
MERR
MD0-63
M
U
X
M
U
X
M
U
X
P0-7
CBI0-7
CBSYN0-7
1
IDT49C466
IDT49C466A
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT49C466/A 64-bit Flow-thruEDC is a high-speed
error detection and correction unit that ensures data integrity
in memory systems. The flow-thru architecture, with separate
system and memory data buses, is ideally suited for pipelined
memory systems.
Implementing a modified Hamming code, the
IDT49C466/A corrects all single bit hard and soft errors, and
detects all double bit errors. The read/write FIFOs can store
up to sixteen words. FIFO full and empty flags indicate
whether additional data can be written to or read from the
EDC.
Check bit generation for partial word writes on byte bound-
aries is supported on the IDT49C466/A.
Diagnostic features include a check bit register, syndrome
registers, a four bit error counter which logs up to 15 errors,
and an error data register which stores the complete error data
word. Parity can be generated and checked on the system
bus by the IDT49C466/A.
11.7
2
IDT49C466/A Flow-thruEDC
TM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
2617 drw 02
ERROR
DETECT
SD
0-63
8
MDILE
Check Bit
Generator
ChkBit
Latch
8
8
SYNDROME
49C466/A 64-Bit Flow-ThruEDC
TM
Diagnostic path
MUX
8
Error data
MCLK
ERROR
CORRECT
MUX
MUX
Latch
Out
MD
SCLK
POWER
SUPPLY
4
17
V
CC
GND
MUX
8
MUX
RBSEL
8
MUX
PARITY
CHECK
SDILE
MCLK
RWBD (Bit 4, Mode Reg)
RS
0-1
Control
Read Fifo
64 wide
Write Fifo
72 wide
Latch
In
SD
8
SCLK
WBSEL
ERR
MD to SD Path
SD to MD Path
Write Back Path
BE
0-7
Syndrome
(on 1st error)
Err Count
Err Type
Chkbit
8-15
16-23
28-29
0-7
24-27
30-37
RWBD (Bit 4, Mode Reg)
Latch
In
MD
Check-bit
Generator
ChkBit
Latch
CBSEL
MUX
8
Latch
Out
SD
SD
SD
MD
GENERATOR
MD
1
0
MD
0-63
CBSYN
0-7
CBI
0-7
P
0-7
BE
0-7
RS
0-1
WBFF
WBEF
ERR
MERR
MDOLE
RBEN
RBREN
RBEF
RBFF
RBHF
SOE
WBEN
WBREN
PERR
CLEAR
from
mode
register
MOE
SDOLE
BYTE MUX
1
0
8
Diagnostic Registers
Syndrome
(on every error)
SYNCLK
Check Bit Injection Mode
DEMUX
1
0
control
1
0
PARITY
GEN
MODE
REGISTER
SD
0-15
MEN
Mode Bit 2
MERR
Mode Bit 5
8
11.7
3
IDT49C466/A Flow-thruEDC
TM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
PQFP
Top View
2617 drw 04
104
105
1
208
156
157
53
52
GND
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
CBSYN5
CBSYN4
GND
CBSYN3
CBSYN2
CBSYN1
CBSYN0
VCC
GND
WBSEL
CBSEL
WBREN
GND
WBEN
SYNCLK
WBFF
WBEF
SD63
SD62
SD61
SD60
P7
BE7
GND SD59
SD58
SD57
SD56
SD55
SD54
MD63
CBSYN7
CBSYN6
SD53
SD52
P6
BE6
SD51
SD50
SD49
SD48
VCC
SD47
GND
SD46
SD45
SD44
BE5
SD42
SD41
SD40
SD39
SD38
SD37
SD36
BE4
GND
P4
SD35
SD34
SD33
SD32
PERR
MCLK
MDOLE
RS1
MEN
GND
RS_0
SDILE
SCLK
SOE
SD31
SD30
SD29
SD28
BE3
P3
SD27
SD26
SD24
SD23
SD22
SD21
SD20
SD25
BE2
P2
SD19
SD17
SD16
GND
P5
SD43
SD18
GND
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2 MD1
MD0 ERR
MERR
CBI7
CBI6
CBI5
CBI4
CBI3
GND
CBI2
CBI1
CBI0
RBEN
RBREN
RBSEL
GND
RBHF
RBEF
RBFF
SD0
SD1
SD2
SD3
GND
P0
BE0
SD4
SD6
SD7
SD8
SD9
SD10
SD5
SD11
BE1
P1
SD13
SD14
SD15
GND
VCC
SD12
MD35
MD13
MD34
MD33
MD32
SDOLE
MD12
MD11
MD10
VCC
MD14
MD15
MD16
MD17
MD18
MD19
GND
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
GND
MD31
MDILE
MOE
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
GND
MD44
PQ208-2
11.7
4
IDT49C466/A Flow-thruEDC
TM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Name
I/O
Description
Data Buses
SD
0-63
I/O
System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output
Enable,
SOE
, is HIGH or Byte Enable, BE
0-7
, is LOW, data can be input. When System Output Enable,
SOE
, is LOW and Byte Enable, BE
0-7
, is HIGH, the SD bus output drivers are enabled.
MD
0-63
I/O
Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (
MOE
HIGH) memory data is input for error detection and correction. Data is output on the Memory Data
Bus, when
MOE
is LOW.
CBI
0-7
I
Check Bit Inputs: interface to the check bit memory.
CBSYN
0-7
O
Check Bit/Syndrome Output: When
MOE
is LOW the generated check bits are output. When
CBSEL is HIGH and
MOE
is HIGH, the syndrome bits are output. The bus is tristated when
MOE
=
1 and CBSEL = 0.
P
0-7
I/O
Parity for bytes 0 to 7: These pins are parity inputs when the corresponding Byte Enable (BE) is LOW
or
SOE
is HIGH, and are used to generate the parity error signal
(
PERR
). These pins are outputs when
the corresponding Byte Enable (BE) is HIGH and
SOE
is LOW.
Control Inputs
SOE
I
System Output Enable: enables system data bus output drivers if the corresponding Byte Enable
(BE
0-7
) is HIGH.
BE
0-7
I
Byte Enable: is used along with
SOE
, to enable the System Data outputs for a particular byte. For
example, if BE
1
is HIGH, the System data outputs for byte 1 (SD
8-15
) are enabled. The BE
0-7
pins also
control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to
the memory data bus. This is used during partial word write operations and writing corrected data back
to memory.
MOE
I
Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and
CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH,
syndrome is selected.
MDILE
I
Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input
latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH.
MDOLE
I
Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH
transition of
MDOLE
. When
MDOLE
is LOW, the MD output latch is transparent.
SDOLE
I
System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch
on the LOW-to-HIGH transition of
SDOLE
. The latch is transparent when
SDOLE
is LOW.
SDILE
I
System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition.
When SDILE is HIGH, the SD input latch is transparent.
WBSEL
I
Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch
is selected.
WBEN
I
Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge.
WBREN
I
Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising
edge.
RS
0-1
I
Reset and Select pins (read and write FIFO FIFOs)
RS
1
RS
0
Function
0
0
Reset 16-deep FIFO or first 8-deep FIFO
0
1
Reset second 8-deep FIFO
1
0
Select 16-deep FIFO or first 8-deep FIFO
1
1
Select second 8-deep FIFO
2617 tbl 01
11.7
5
IDT49C466/A Flow-thruEDC
TM
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGES
Pin Name
I/O
Description
RBSEL
I
Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output
latch). When LOW, the MD output latch is selected.
RBEN
I
Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH
transition of the memory clock.
RBREN
I
Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH
transition of SCLK
CBSEL
I
Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is
enabled. When CBSEL is LOW,
MOE
controls the buffer.
MEN
I
Mode Enable Input: when LOW, SD
0-15
is loaded into the EDC mode register on the LOW-to-HIGH
transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure
4.
Clock Inputs
MCLK
I
Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO
when
RBEN
is LOW. Data is read from the write FIFO when
WBREN
is LOW, on the LOW-to-HIGH
transition of MCLK.
SCLK
I
System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when
RBREN
is LOW. Data on the system data bus is written into the write FIFO when
WBEN
is LOW on
the LOW-to-HIGH transition of SCLK. Clocks data into mode register when
MEN
is LOW.
SYNCLK
I
Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is
incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset,
SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One
of the syndrome registers has new data clocked in on every SYNCLK rising edge.
Status Outputs
WBEF
O
Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the
WBEF
goes LOW.
WBFF
O
Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset,
WBFF
goes HIGH.
RBEF
O
Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the
RBEF
goes LOW.
RBHF
O
Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-
deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The
flag will return HIGH when less than eight (or four) data words are in the FIFO.
RBFF
O
Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset,
RBFF
goes HIGH.
ERR
O
Error Flag: when
ERR
is LOW, a data error is indicated. The
ERR
is not latched internally.
MERR
O
Multiple Error Flag: when
MERR
is LOW, a multiple data error is indicated. The
MERR
is not latched
internally.
PERR
O
Parity Error Flag: when LOW, indicates a parity error on the system data bus input.
Power Supply
V
CC
P
Power Supply Voltage.
GND
P
Ground.
2617 tbl 02
PIN DESCRIPTION (Continued)
PDF 
ZIP