MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
1
JUNE 2002
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5426/3
FEATURES:
Equivalent to AMD's Am29823 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
IDT54/74FCT823A equivalent to FASTTM speed
IDT54FCT823B 25% faster than FAST
IDT74FCT823C 40% faster than FAST
Buffered common Clock Enable (EN) and Asynchronous Clear
Input (CLR)
I
OL
= 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output compatibility
CMOS output level compatible
Substantially lower input current levels than AMD's bilopar
Am29800 series (5
A max.)
MIlitary product compliant to MIL-STD-883, Class B
Available in the following packages:
Commercial: SOIC
Military: CERDIP, LCC
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT823 series is built using an advanced dual metal CMOS
technology. The FCT823 bus interface registers are designed to eliminate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear
(CLR) ideal for parity bus interfacing in high-performance microprogram-
med systems.
The FCT823 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
IDT54/74FCT823A/B/C
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
D
CP
Q
Q
CL
D
N
D
0
D
CP
Q
Q
CL
EN
CLR
CP
O E
Y
0
Y
N
14
11
13
1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
PIN CONFIGURATION
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
2
3
1
20
19
18
15
16
9
10
D
6
D
7
D
2
D
5
D
3
D
4
D
8
23
22
24
21
17
5
6
7
4
8
D
0
V
CC
CP
OE
13
14
11
12
D
1
GND
CLR
Y
6
Y
7
Y
2
Y
5
Y
3
Y
4
Y
8
Y
0
Y
1
EN
15
16
N
C
12
13
14
G
N
D
D
8
17
18
C
P
E
N
Y
8
N
C
V
C
C
O
E
D
1
D
0
Y
0
Y
1
Y
3
NC
Y
4
5
6
8
7
9
10
11
1
28
4
3
2
27
26
25
24
22
23
21
20
19
D
5
NC
D
3
D
4
D
2
D
7
D
6
INDEX
Y
5
C
L
R
Y
2
Y
7
Y
6
LOGIC SYMBOL
CP
D
OE
Q
D
CP
Y
9
9
EN
CLR
CLR
EN
Symbol
Rating
Commercial
Military
Unit
V
TERM
(2)
Terminal Voltage
0.5 to +7
0.5 to +7
V
with Respect to GND
V
TERM
(3)
Terminal Voltage
0.5 to V
CC
0.5 to V
CC
V
with Respect to GND
T
A
Operating Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature under BIAS
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output Current
120
120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
Pin Name
I/O
Description
Dx
I
D flip-flop data inputs
CLR
I
For both inverting and non-inverting registers, when
the clear input is LOW and OE is LOW, the Q
x
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
C P
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Y x
O
Register 3-state outputs
EN
I
Clock Enable. When the clock enable is LOW, data
on the D
I
input is transferred to the Q
I
output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change state,
regardless of the data or clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the OE
input is LOW, the TRUE register data is present at the
Yx
outputs.
PIN DESCRIPTION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
3
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
V
I
= V
CC
--
--
5
V
CC
= Max.
V
I
= 2.7V
--
--
5
(4)
A
I
IL
Input LOW Current
V
I
= 0.5V
--
--
5
(4)
V
I
= GND
--
--
5
I
OZH
V
O
= V
CC
--
--
10
Off State (High Impedance)
V
CC
= Max.
V
O
= 2.7V
--
--
10
(4)
A
I
OZL
Output Current
V
O
= 0.5V
--
--
10
(4)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
75
120
--
mA
V
OH
Output HIGH Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= 32
A
V
HC
V
CC
--
V
CC
= Min
I
OH
= 300
A
V
HC
V
CC
--
V
V
IN
= V
IH
or V
IL
I
OH
= 15mA MIL
2.4
4.3
--
I
OH
= 24mA COM'L
2.4
4.3
--
V
OL
Output LOW Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
A
--
GND
V
LC
V
CC
= Min
I
OL
= 300
A
--
GND
V
LC
(4)
V
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL
--
0.3
0.5
I
OL
= 48mA COM'L
--
0.3
0.5
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0C to +70C, V
CC
= 5.0V 5%, Military: T
A
= -55C to +125C, V
CC
= 5.0V 10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH Transition
FUNCTION TABLE
(1)
Inputs
Internal/
Outputs
OE
CLR
EN
Dx
CP
Qx
Yx
Function
H
H
L
L
L
Z
High Z
H
H
L
H
H
Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
H
H
H
X
X
N C
Z
Hold
L
H
H
X
X
N C
N C
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
L
H
L
L
L
L
L
H
L
H
H
H
MILITARY AND COMMERCIAL TEMPERATURE RANGES
4
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.2
1.5
mA
V
IN
V
HC
; V
IN
V
LC
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
2
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
V
HC
--
0.15
0.25
mA/
Current
(4)
Outputs Open
V
IN
V
LC
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
V
HC
--
1.7
4
mA
Outputs Open
V
IN
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
OE = EN = GND
V
IN
= 3.4V
--
2.2
6
One Bit Toggling
V
IN
= GND
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
V
IN
V
HC
--
4
7.8
(5)
Outputs Open
V
IN
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
V
IN
= 3.4V
--
6.2
16.8
(5)
OE = EN = GND
V
IN
= GND
at fi = 2.5MHz
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + fiNi)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
54/74FCT823A
54FCT823B
74FCT823C
Com'l.
Mil.
Mil.
Com'l.
Symbol Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
--
10
--
11.5
--
8.5
--
6
ns
t
PHL
CP to Yx (OE = LOW)
R
L
= 500
C
L
= 300pF
(3)
--
20
--
20
--
16
--
12.5
R
L
= 500
t
PZH
Output Enable Time,
C
L
= 50pF
--
12
--
13
--
9
--
7
ns
t
PZL
OE to Yx
R
L
= 500
C
L
= 300pF
(3)
--
23
--
25
--
16
--
12.5
R
L
= 500
t
PHZ
Output Disable Time,
C
L
= 5pF
(3)
--
7
--
8
--
7
--
6.2
ns
t
PLZ
OE to Yx
R
L
= 500
C
L
= 50pF
--
8
--
9
--
8
--
6.5
R
L
= 500
t
SU
Set-up Time HIGH or LOW, Dx to CP
C
L
= 50pF
4
--
4
--
3
--
3
--
ns
Set-up Time HIGH or LOW, EN to CP
R
L
= 500
t
H
Hold Time HIGH or LOW, Dx to CP
2
--
2
--
1.5
--
1.5
--
ns
t
H
Hold Time HIGH or LOW, EN to CP
2
--
2
--
0
--
0
--
ns
t
PHL
Propagation Delay, CLR to Yx
--
14
--
15
--
9.5
--
8
ns
t
REM
Recovery Time, CLR to CP
6
--
7
--
6
--
6
--
ns
t
W
CP Pulse Width HIGH or LOW
7
--
7
--
6
--
6
--
ns
t
W
CLR Pulse Width HIGH or LOW
6
--
7
--
6
--
6
--
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
Pulse
Generator
R
T
D.U.T
.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; Z
O
50; t
F
2.5ns; t
R
2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCE CMOS BUFFER
7
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
XX
Package
X
Process
SO
Commercial Options
Small Outline IC
High Performance CMOS Bus
Interface Register, 9-Bit
54
74
55C to +125C
40C to +85C
D
L
Military Options
CERDIP
Leadless Chip Carrier
Blank
B
Commercial
MIL-STD-883, Class B
FCT
823A
823B
823C
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
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