Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.4
DSC-3032/6
IDT54/74FCT16260AT/CT/ET
IDT54/74FCT162260AT/CT/ET
1
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
FEATURES:
Common features:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for
ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
1
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40
C to +85
C
V
CC
= 5V
10%
Features for FCT16260AT/CT/ET:
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
C
Features for FCT162260AT/CT/ET:
Balanced Output Drivers:
24mA (commercial),
16mA (military)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25
C
DESCRIPTION:
The FCT16260AT/CT/ET and the FCT162260AT/CT/ET
Tri-Port Bus Exchangers are high-speed 12-bit latched bus
multiplexers/transceivers for use in high-speed microproces-
sor applications. These Bus Exchangers support memory
interleaving with latched outputs on the B ports and address
multiplexing with latched inputs on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the
B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B)
inputs control data storage. When a latch-enable input is
HIGH, the latch is transparent. When a latch-enable input is
LOW, the data at the input is latched and remains latched until
the latch enable input is returned HIGH. Independent output
enables (
OE1B
and
OE2B
) allow reading from one port while
writing to the other port.
The FCT16260AT/CT/ET are ideally suited for driving high
capacitance loads and low impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162260AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times - reduc-
ing the need for external series terminating resistors.
A-1B
LATCH
LEA1B
LE1B
LE2B
12
M
U
X
12
OE1B
12
A
1:12
1B-A
LATCH
1B
1:12
12
12
12
2B-A
LATCH
12
12
A-2B
LATCH
LEA2B
12
2B
1:12
OE2B
OEA
SEL
1
0
3032 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
5.4
2
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN CONFIGURATIONS
OE2B
2B
5
2B
6
GND
2B
7
2B
8
V
CC
2B
9
2B
10
2B
4
2B
11
2B
12
1B
12
1B
11
GND
1B
10
1B
9
V
CC
1B
8
GND
LEA2B
1B
6
1B
7
1B
5
GND
1B
4
OE1B
LEA1B
OEA
LE1B
2B
3
GND
2B
2
2B
1
V
CC
A
1
A
2
GND
A
3
A
4
A
5
A
6
GND
A
7
A
8
V
CC
A
9
1B
3
A
11
A
10
1B
1
GND
1B
2
SEL
A
12
LE2B
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
CERPACK
TOP VIEW
E56-1
3032 drw 03
OEA
LE1B
GND
2B
2
V
CC
A
3
A
6
A
7
GND
A
12
2B
3
2B
1
A
1
A
2
GND
A
4
A
5
A
8
A
9
A
10
V
CC
1B
1
A
11
1B
2
LEA2B
2B
4
GND
2B
5
2B
6
V
CC
2B
7
2B
8
GND
2B
10
2B
11
2B
12
1B
11
1B
10
GND
1B
9
V
CC
1B
6
1B
8
2B
9
1B
12
1B
7
1B
5
OE2B
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SSOP/
TSSOP/TVSOP
TOP VIEW
SO56-1
SO56-2
SO56-3
LE2B
GND
SEL
1B
3
OE1B
GND
1B
4
LEA1B
49
56
55
50
51
52
53
54
3032 drw 02
5.4
3
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN DESCRIPTION
Signal
I/O
Description
A
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1B
(1:12)
I/O
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
2B
(1:12
)
I/O
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
LEA1B
I
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on
the HIGH to LOW transition of LEA1B.
LEA2B
I
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on
the HIGH to LOW transition of LEA2B.
LE1B
I
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched
on the HIGH to LOW transition of LE1B.
LE2B
I
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched
on the HIGH to LOW transition of LE2B.
SEL
I
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables
data transfer from 2B Port to A Port.
OEA
I
Output Enable for A Port (Active LOW).
OE1B
I
Output Enable for 1B Port (Active LOW).
OE2B
I
Output Enable for 2B Port (Active LOW).
3032 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
FUNCTION TABLES
(2)
3032 tbl 04
Inputs
Output
1B
2B
SEL
LE1B
LE2B
OEA
OEA
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A
(1)
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A
(1)
X
X
X
X
X
H
Z
Inputs
Outputs
A
LEA1B LEA2B
OE1B
OE1B OE2B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
B
(1)
L
H
L
L
L
L
B
(1)
H
L
H
L
L
B
(1)
H
L
L
H
L
L
B
(1)
L
X
L
L
L
L
B
(1)
B
(1)
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
3032 tbl 05
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH Transition
Symbol
Description
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect to
GND
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage with Respect to
GND
0.5 to
V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120 mA
3032 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE
(T
A
= +25
C, F = 1.0MH
Z
)
3032 tbl 03
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input
Capacitance
V
IN
= 0V
3.5
6.0
pF
C
I/O
I/O
Capacitance
V
OUT
= 0V
3.5
8.0
pF
NOTE:
1. This parameter is measured at characterization but not tested.
5.4
4
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 40
C to +85
C, V
CC
= 5.0V
10%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
I L
Input LOW Current (Input pins)
(5)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
225
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
5
500
A
3032 tbl 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT16260T
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
O
Output Drive Current
V
CC
= Max., V
O
= 2.5V
(3)
50
--
180
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 3mA
2.5
3.5
--
V
V
IN
= V
IH
or V
IL
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.4
3.5
--
V
I
OH
= 24mA MIL.
I
OH
= 32mA COM'L.
(4)
2.0
3.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
--
0.2
0.55
V
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
3032 tbl 07
OUTPUT DRIVE CHARACTERISTICS FOR FCT162260T
3032 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
5
A at T
A
= 55
C.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or
V
IL,
V
OUT
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 16mA MIL.
I
OH
= 24mA COM'L.
2.4
3.3
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
--
0.3
0.55
V
5.4
5
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
POWER SUPPLY CHARACTERISTICS
3032 tbl 09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
1.5
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
60
100
A/
MHz
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fi = 10MHz
V
IN
= V
CC
V
IN
= GND
--
0.6
1.5
mA
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
V
IN
= 3.4V
V
IN
= GND
--
0.9
2.3
V
CC
= Max.
Outputs Open
fi = 2.5MHz
V
IN
= V
CC
V
IN
= GND
--
1.8
3.5
(5)
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
Twelve Input Bits Toggling
Twelve Output Bits Toggling
V
IN
= 3.4V
V
IN
= GND
--
4.8
12.5
(5)
5.4
6
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
3032 tbl 10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
FCT16260AT/162260AT
FCT16260CT/162260CT
FCT16260ET/162260ET
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
t
PLH
t
PHL
Propagation Delay
A
X
to 1B
X
or Ax to 2B
X
C
L
= 50pF
R
L
= 500
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
3.6
--
--
ns
t
PLH
t
PHL
Propagation Delay
1B
X
to A
X
or 2B
X
to A
X
1.5
5.6
1.5
5.9
1.5
5.0
1.5
5.4
1.5
3.6
--
--
ns
t
PLH
t
PHL
Propagation Delay
LE
X
B to A
X
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4.0
--
--
ns
t
PLH
t
PHL
Propagation Delay
LEA1B to 1B
X
or
LEA2B to 2B
X
1.5
4.7
1.5
5.2
1.5
4.4
1.5
4.8
1.5
4.0
--
--
ns
t
PLH
t
PHL
Propagation Delay
SEL to A
X
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4.0
--
--
ns
t
PZH
t
PZL
Output Enable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
1.5
5.7
1.5
6.1
1.5
5.1
1.5
5.4
1.5
4.4
--
--
ns
t
PHZ
t
PLZ
Output Disable Time
OEA
to A
X
,
OE1B
to 1B
X
, or
OE2B
to 2B
X
1.5
4.4
1.5
4.8
1.5
4.0
1.5
4.4
1.5
4.0
--
--
ns
t
SU
Set-Up Time, HIGH or LOW
Data to Latch
1.5
--
1.5
--
1.0
--
1.0
--
1.0
--
--
--
ns
t
H
Hold Time, Latch to Data
1.0
--
1.5
--
1.0
--
1.5
--
1.0
--
--
--
ns
t
W
Pulse Width, Latch HIGH
(4)
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
--
--
ns
t
SK
(o) Output Skew
(3)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
--
ns
5.4
7
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
3032 lnk 04
3032 lnk 06
SWITCH POSITION
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
3032 lnk 08
3032 lnk 05
3032 lnk 07
3032 lnk 11
5.4
8
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
ORDERING INFORMATION
3032 drw 09
X
Temperature
Range
XXXX
Device
Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16260AT
16260CT
16260ET
162260AT
162260CT
162260ET
12-Bit Tri-Port Bus Exchanger
-55
C to +125
C
-40
C to +85
C
54
74
IDT
FCT
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