1
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
JUNE 2002
IDT74FCT162373AT/CT/ET
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT
TRANSPARENT
LATCH
DESCRIPTION:
The FCT162373T 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal for
temporary storage of data. It can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 8-bit latches, or one 16-bit latch.
Flow-through organization of signal pins simplifies layout. All inputs are designed
with hysteresis for improved noise margin.
The FCT162373T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
timesreducing the need for external series terminating resistors. The
FCT162373T is a plug-in replacement for the FCT16373T and ABT16373 for
on-board interface applications.
2
O
1
2
OE
2
LE
2
D
1
TO SEVEN OTHE R C HANN ELS
C
D
1
OE
1
LE
1
O
1
1
D
1
TO SEVEN OTHE R CHANN ELS
C
D
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5455/3
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1A (max.)
V
CC
= 5V 10%
Balanced Output Drivers: 24mA
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
2
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
1
O
1
GND
1
O
3
V
CC
1
OE
GND
2
O
2
GND
V
CC
GND
1
O
2
1
O
4
1
O
5
1
O
6
1
O
7
1
O
8
2
O
1
2
O
3
2
O
4
2
O
5
2
O
7
2
O
8
2
O
6
2
OE
1
LE
1
D
1
1
D
2
GND
1
D
3
1
D
4
V
CC
1
D
5
1
D
6
1
D
7
1
D
8
2
D
1
2
D
2
2
D
3
2
D
4
V
CC
2
D
5
2
D
7
2
D
8
2
D
6
2
LE
GND
GND
GND
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
ABSOLUTE MAXIMUM RATINGS
(1)
(1)
(1)
(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Pin Names
Description
xDx
Data Inputs
xLE
Latch Enable Input (Active HIGH)
xOE
Outputs Enable Input (Active LOW)
xOx
3-State Outputs
PIN DESCRIPTION
NOTE:
1. H = HIGH Voltage Level
X = Don't Care
L = LOW Voltage Level
Z = High-Impedance
Inputs
Outputs
xDx
xLE
xOE
xOx
H
H
L
H
L
H
L
L
X
X
H
Z
FUNCTION TABLE
(1)
3
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
IL
Input LOW Current (Input pins)
(5)
V
CC
= Max.
V
I
= GND
--
--
1
A
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= Max.
--
5
500
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V
,
V
IN =
V
IH
or
V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V
,
V
IN =
V
IH
or
V
IL,
V
O
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min
I
OH
= 24mA
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min
I
OL
= 24mA
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
OUTPUT DRIVE CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is 5A at T
A
= 55C.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
--
0.5
1.5
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max.
V
IN
= V
CC
--
60
100
A/
Current
(4)
Outputs Open
V
IN
= GND
MHz
xOE = GND
One Input Togging
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
0.6
1.5
mA
Outputs Open
V
IN
= GND
fi = 10MHz
50% Duty Cycle
V
IN
= 3.4V
--
0.9
2.3
xOE = GND
V
IN
= GND
xLE = V
CC
One Bit Togging
V
CC
= Max.
V
IN
= V
CC
--
2.4
4.5
(5)
Outputs Open
V
IN
= GND
fi = 2.5MHz
50% Duty Cycle
xOE = GND
V
IN
= 3.4V
--
6.4
16.5
(5)
xLE = V
CC
V
IN
= GND
Sixteen Bits Togging
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
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IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
74FCT162373AT
74FCT162373CT
74FCT162373ET
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
1.5
5.2
1.5
4.2
1.5
3.4
ns
t
PHL
xDx to xOx
R
L
= 500
t
PLH
Propagation Delay
2
8.5
2
5.5
1.5
3.7
ns
t
PHL
xLE to xOx
t
PZL
Output Enable Time
1.5
6.5
1.5
5.5
1.5
4.4
ns
t
PZH
t
PHZ
Output Disable Time
1.5
5.5
1.5
5
1.5
3.6
ns
t
PLZ
t
SU
Set-up Time HIGH or LOW, xDx to xLE
2
--
2
--
1
--
ns
t
H
Hold Time HIGH or LOW, xDx to xLE
1.5
--
1.5
--
1
--
ns
t
W
xLE Pulse Width HIGH
5
--
5
--
3
(4)
--
ns
t
SK(o)
Output Skew
(3)
--
0.5
--
0.5
--
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
6
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
Pulse
G enerator
R
T
D.U.T.
V
CC
V
IN
C
L
V
O UT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHR ONO US C O NTRO L
PRESET
CLEAR
ETC.
SYNCHRO NO US CO NTRO L
t
SU
t
H
t
RE M
t
SU
t
H
PRESET
CLEAR
CLO CK ENABLE
ETC.
HIGH-LOW -HIG H
PULSE
LO W -HIG H-LO W
PULSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRANSITIO N
3V
1.5V
0V
1.5V
V
OH
t
PLH
O UTPUT
O PPO SITE PHASE
INPUT TRANSITIO N
3V
1.5V
0V
t
PLH
t
PH L
t
PH L
V
OL
CONTRO L
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NO RMALLY
LO W
OUTPUT
NO RMALLY
HIG H
SW ITCH
CLOSED
SW ITCH
O PEN
V
O L
0.3V
0.3V
t
PLZ
t
PZL
t
P ZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
O H
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
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IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
XX
Package
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
16-Bit Transparent Latch
74
40C to +85C
162
Double-Density, 5 Volt, Balanced Drive
FCT
XXX
Family
373AT
373CT
373ET
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
3/26/2002 Removed standard speed grade
4/18/2002 Switching Cha. table
6/20/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY
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