PRODUCT PREVIEW
Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.9
DSC-3247/-
1
FAST CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74FCT16601AT/CT/ET
IDT74FCT162601AT/CT/ET
PRODUCT PREVIEW
bit registered transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power 18-bit reg-
istered bus transceivers combine D-type latches and D-type
flip-flops to allow data flow in either direction in a transparent,
latched or clocked mode. Each direction has an independent
latch enable, an independent clock with a clock enable, and an
independent output enable. The package is organized with a
flow-through signal pin organization to ease board layout. All
inputs are designed with hysteresis for improved noise mar-
gin.
This transceiver is ideally suited for high speed memory
interfaces which utilize high speed synchronous writes, by
clocking the data into a high speed register. Reads can then
be performed in a transparent or latched mode utilizing the
same transceiver.
The FCT16601AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162601AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall timesreducing
the need for external series terminating resistors. The
FCT162601AT/CT/ET are plug-in replacements for the
FCT16601AT/CT/ET and ABT16601 for on-board bus inter-
face applications.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LEAB
CLKAB
LEBA
CLKBA
CLKENAB
OEAB
A
1
TO 17 OTHER CHANNELS
OEBA
CE
1D
C1
CLK
CE
1D
C1
CLK
CLKENBA
1
56
55
2
28
30
29
27
3
54
B
1
3247 drw 01
FEATURES:
Common features:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for
ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
1
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40
C to +85
C
V
CC
= 5V
10%
Features for FCT16601AT/CT/ET:
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit "live insertion"
Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
C
Features for FCT162601AT/CT/ET:
Balanced Output Drivers:
24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25
C
DESCRIPTION:
The FCT16601AT/CT/ET and FCT162601AT/CT/ET 18-
FUNCTIONAL BLOCK DIAGRAM
5.9
2
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PRODUCT PREVIEW
PIN CONFIGURATIONS
3247 drw 02
ABSOLUTE MAXIMUM RATINGS
(1)
CLKENAB
B
2
B
3
GND
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
10
B
11
GND
B
12
B
13
V
CC
B
14
GND
CLKAB
B
16
B
15
B
17
GND
B
18
CLKBA
CLKENBA
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GND
A
17
LEBA
A
15
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SSOP/
TSSOP/TVSOP
TOP VIEW
SO56-1
SO56-2
SO56-3
29
30
31
32
25
26
27
28
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB
A to B Clock Enable Input
CLKENBA
B to A Clock Enable Input
3247 tbl 01
FUNCTION TABLE
(1,4)
Inputs
Outputs
CLKENAB
CLKENAB
OEAB
OEAB
LEAB
CLKAB
A
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B0
(2)
L
L
L
L
L
L
L
L
H
H
L
L
L
L
X
B0
(2)
L
L
L
H
X
B0
(3)
NOTES:
3247 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
=
LOW-to-HIGH Transition
Symbol
Description
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect to
GND
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage with Respect to
GND
0.5 to
V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120 mA
3247 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
NOTE:
1. This parameter is measured at characterization but not tested.
3247 lnk 04
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input
Capacitance
V
IN
= 0V
3.5
6.0
pF
C
I/O
I/O
Capacitance
V
OUT
= 0V
3.5
8.0
pF
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
5.9
3
PRODUCT PREVIEW
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 40
C to +85
C, V
CC
= 5.0V
10%
3247 lnk 06
3247 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16601T
OUTPUT DRIVE CHARACTERISTICS FOR FCT162601T
3247 lnk 07
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current (Input pins)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
--
--
1
I
I L
Input LOW Current (Input pins)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
225
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
5
500
A
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
O
Output Drive Current
V
CC
= Max., V
O
= 2.5V
(3)
50
--
180
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 3mA
2.5
3.5
--
V
V
IN
= V
IH
or V
IL
I
OH
= 15mA
2.4
3.5
--
V
I
OH
= 32mA
(4)
2.0
3.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 64mA
--
0.2
0.55
V
I
OFF
Input/Output Power Off Leakage
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or
V
IL,
V
OUT
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 24mA
2.4
3.3
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 24mA
--
0.3
0.55
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5.9
4
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PRODUCT PREVIEW
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
1.5
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
75
120
A/
OEAB
= V
CC
OEBA
= GND
V
IN
= GND
MHz
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
0.8
1.7
mA
f
CP
= 10MHz (CLKBA)
V
IN
= GND
50% Duty Cycle
OEAB
= V
CC
OEBA
= GND
LEAB = GND
V
IN
= 3.4V
--
1.3
3.2
CLKENBA
= GND
V
IN
= GND
One Bit Toggling
f
i
=
5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
3.8
6.5
(5)
f
CP
= 10MHz (CLKBA)
V
IN
= GND
50% Duty Cycle
OEAB
= V
CC
OEBA
= GND
LEAB = GND
V
IN
= 3.4V
--
8.5
20.8
(5)
CLKENBA
= GND
V
IN
= GND
Eighteen Bits Toggling
f
i
=
2.5MHz
50% Duty Cycle
3247 tbl 09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
5.9
5
PRODUCT PREVIEW
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16601AT/
FCT162601AT
FCT16601CT/
FCT162601CT
FCT16601ET/
FCT162601ET
Symbol
Parameter
Condition
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
f
MAX
CLKAB or CLKBA frequency
(4)
C
L
= 50pF
--
150
--
150
--
150
MHz
t
PLH
t
PHL
Propagation Delay
Ax to Bx or Bx to Ax
R
L
= 500
1.5
4.9
1.5
4.4
1.5
3.8
ns
t
PLH
t
PHL
Propagation Delay
LEBA to Ax, LEAB to Bx
1.5
5.2
1.5
4.7
1.5
4.2
ns
t
PLH
t
PHL
Propagation Delay
CLKBA to Ax, CLKAB to Bx
1.5
4.7
1.5
4.5
1.5
4.2
ns
t
PZH
t
PZL
Output Enable Time
OEBA
to Ax,
OEAB
to Bx
1.5
5.8
1.5
5.3
1.5
4.8
ns
t
PHZ
t
PLZ
Output Disable Time
OEBA
to Ax,
OEAB
to Bx
1.5
6.2
1.5
5.7
1.5
5.2
ns
t
SU
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
4.0
--
3.0
--
2.4
--
ns
t
H
Hold Time HIGH or LOW
Ax after CLKAB, Bx after CLKBA
0
--
0
--
0
--
ns
t
SU
Set-up Time HIGH or LOW Clock LOW
1.0
--
1.0
--
1.0
--
ns
Ax to LEAB, Bx to LEBA
Clock HIGH
2.5
--
2.0
--
1.5
--
ns
t
H
Hold Time, HIGH or LOW
Ax after LEAB, Bx after LEBA
2.0
--
1.5
--
0.5
--
ns
t
SU
Set-up Time,
CLKEN
to CLK
2.5
--
2.5
--
2.0
--
ns
t
H
Hold Time,
CKLEN
after CLK
0
--
0
--
0
--
ns
t
W
LEAB or LEBA Pulse Width
HIGH
(4)
2.5
--
2.5
--
2.5
--
ns
t
W
CLKAB or CLKBA Pulse Width
HIGH or LOW
(4)
3.0
--
3.0
--
3.0
--
ns
t
SK
(o) Output Skew
(3)
--
0.5
--
0.5
--
0.5
ns
NOTES:
3247 tbl 09
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
PDF 
ZIP