MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
6.20
DSC-2634/9
Integrated Device Technology, Inc.
1
FAST CMOS OCTAL
TRANSCEIVER/
REGISTERS (3-STATE)
FEATURES:
Common features:
Low input and output leakage
1
A (max.)
Extended commercial range of 40
C to +85
C
CMOS power levels
True TTL input and output compatibility
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, TSSOP,
CERPACK and LCC packages
Features for FCT646T/648T/652T:
Std., A, C and D speed grades
High drive outputs (-15mA I
OH
, 64mA I
OL
)
Power off disable outputs permit "live insertion"
Features for FCT2646T/2652T:
Std., A, and C speed grades
Resistor outputs
(-15mA I
OH
, 12mA I
OL
Com.)
(-12mA I
OH
, 12mA I
OL
Mil.)
Reduced system switching noise
DESCRIPTION:
The FCT646T/FCT2646T/FCT648T/FCT652T/2652T con-
sist of a bus transceiver with 3-state D-type flip-flops and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage regis-
ters.
The FCT652T/FCT2652T utilize GAB and
GBA
signals to
control the transceiver functions. The FCT646T/FCT2646T/
FCT648T utilize the enable control (
G
) and direction (DIR)
pins to control the transceiver functions.
SAB and SBA control pins are provided to select either real-
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-
time data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (CPAB or CPBA), regardless of the select or
enable control pins.
The FCT26xxT have balanced drive outputs with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
2634 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT
IDT54/74FCT648T/AT/CT
IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT
A1
G
DIR
CPBA
SBA
CPAB
SAB
GBA
GAB
1 OF 8 CHANNELS
B REG
A REG
B1
1D
C1
C1
1D
TO 7 OTHER CHANNELS
646/2646/652/2652
ONLY
646/2646/652/2652
ONLY
IDT54/74FCT652/2652
ONLY
IDT54/74FCT646/2646/648
ONLY
FUNCTIONAL BLOCK DIAGRAM
6.20
2
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
2634 drw 05
PIN DESCRIPTION
2634 tbl 01
2634 drw 04
2634 drw 02
Pin Names
Description
A
1
- A
8
Data Register A Inputs
Data Register B Outputs
B
1
- B
8
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Output Data Source Select Inputs
DIR,
G
Output Enable Inputs (646/648)
GAB,
GBA
Output Enable Inputs (652)
CPAB
SAB
DIR
A
1
A
2
A
3
A
4
A
5
A
6
GND
CPBA
SBA
G
B
1
B
2
B
4
B
3
B
5
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
SO24-9*
&
E24-1
11
12
21
22
23
24
A
7
A
8
B
6
B
7
DIP/SOIC/SSOP/
QSOP/TSSOP/CERPACK
TOP VIEW
B
8
* FCT646/2646T/AT/CT/DT only
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
GND
CPBA
SBA
GBA
B
1
B
2
B
4
B
3
B
5
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
&
E24-1
11
12
21
22
23
24
A
7
A
8
B
6
B
7
DIP/SOIC/SSOP/
QSOP/CERPACK
TOP VIEW
B
8
* FCT652/2652T/AT/CT/DT only
INDEX
LCC
TOP VIEW
3
2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
12 13
21
22
23
24
25
26
27
28
L28-1
A
1
A
2
A
3
NC
A
4
A
5
A
6
G
B
1
B
2
NC
B
3
B
4
B
5
DIR
SAB
CPAB
NC
V
CC
CPBA
SBA
A
7
A
8
GND
NC
B
8
B
7
B
6
INDEX
LCC
TOP VIEW
3
2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
12 13
21
22
23
24
25
26
27
28
L28-1
A
1
A
2
A
3
NC
A
4
A
5
A
6
GBA
B
1
B
2
NC
B
3
B
4
B
5
GAB
SAB
CPAB
NC
V
CC
CPBA
SBA
A
7
A
8
GND
NC
B
8
B
7
B
6
FCT652/FCT2652T
FCT646/FCT2646T
FCT648
2634 drw 03
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
3
FUNCTION TABLE (646/648)
FUNCTION TABLE (652)
Inputs
Data I/O
(1)
Operation or Function
G
G
DIR
CPAB
CPBA
SAB
SBA
A
1
- A
8
B
1
- B
8
FCT646T/FCT2646T
FCT648T
H
H
X
X
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
Isolation
Store A and B Data
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time
B
Data to A Bus
Stored
B
Data to A Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
Real-Time
A
Data to B Bus
Stored
A
Data to B Bus
2634 tbl 02
Inputs
Data I/O
Operation or Function
GAB
GBA
GBA
CPAB
CPBA
SAB
SBA
A
1
- A
8
B
1
- B
8
FCT652T/FCT2652T
L
L
H
H
H or L
H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
X
H
H
H
H or L
X
X
(2)
X
X
Input
Input
Unspecified
(1)
Output
Store A, Hold B
Store A in Both Registers
L
L
X
L
H or L
X
X
X
X
(2)
Unspecified
(1)
Output
Input
Input
Hold A, Store B
Store B in Both Registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and Stored B Data to A Bus
NOTES:
2634 tbl 03
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = HIGH, L = LOW, X = Don't Care,
= LOW-to-HIGH transition.
3.
A
in B Register.
4.
B
in A Register.
6.20
4
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRANSFER STORES
DATA TO A AND/OR B
STORAGE FROM
A AND/OR B
2634 drw 08
REAL-TIME TRANSFER
BUS B TO A
2634 drw 06
REAL-TIME TRANSFER
BUS A TO B
2634 drw 07
2634 drw 09
NOTE:
1. 646/2646/648 cannot transfer data to A bus and B bus simultaneously.
652/2652
GAB
GBA
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
646/2646/
648
DIR
G
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
BUS
B
BUS
A
BUS
A
BUS
B
652/2652
GAB
GBA
CPAB
CPBA
SAB
SBA
H
H
X
X
L
X
646/2646/
648
DIR
G
CPAB
CPBA
SAB
SBA
H
L
X
X
L
X
BUS
A
BUS
B
652/2652
GAB
GBA
CPAB
CPBA
SAB
SBA
X
H
X
X
X
L
X
X
X
X
L
H
X
X
646/2646/
648
DIR
G
CPAB
CPBA
SAB
SBA
H
L
X
X
X
L
L
X
X
X
X
H
X
X
BUS
A
BUS
B
652/2652
GAB
GBA
CPAB
CPBA
SAB
SBA
H
L
H or
H or
H
H
646/2646/
648
DIR
G
CPAB
CPBA
SAB
SBA
L
L
X
H or
X
H
H
L
H or
X
H
X
(1)
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
5
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
(1)
Conditions
Typ.
Max. Unit
C
IN
Input
Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
8
12
pF
2634 lnk 05
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol
Description
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect to
GND
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage with Respect to
GND
0.5 to
V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
2634 lnk 04
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 40
C to +85
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
2634 lnk 06
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
I L
Input LOW Current
(4)
V
I
= 0.5V
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
OUTPUT DRIVE CHARACTERISTICS FOR FCT646T/648T/652T
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 6mA MIL.
I
OH
= 8mA COM'L.
2.4
3.3
--
V
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.0
3.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
--
0.3
0.55
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
2634 lnk 05
6.20
6
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUT DRIVE CHARACTERISTICS FOR FCT2646T/2652T
2634 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
5
A at T
A
= 55
C.
5. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
2634 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or
V
IL,
V
OUT
= 1.5V
(3)
16
48
--
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
16
48
--
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or
V
IL
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.4
3.3
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 12mA
--
0.3
0.50
V
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
GAB =
GBA
= GND or
V
IN
= V
CC
V
IN
= GND
FCTxxxT
--
0.15
0.25
mA/
MHz
G
= DIR = GND
One Input Toggling
50% Duty Cycle
FCT2xxxT
--
0.06
0.12
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
V
IN
= V
CC
V
IN
= GND
FCTxxxT
--
1.5
3.5
mA
f
CP
= 10MHz
50% Duty Cycle
FCT2xxxT
--
0.6
2.2
GAB =
GBA
= GND or
G
= DIR = GND
V
IN
= 3.4
V
IN
= GND
FCTxxxT
--
2.0
5.5
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
FCT2xxxT
1.1
4.2
V
CC
= Max.
Outputs Open
V
IN
= V
CC
V
IN
= GND
FCTxxxT
--
3.8
7.3
(5)
f
CP
= 10MHz
50% Duty Cycle
FCT2xxxT
--
1.5
4.0
(5)
GAB =
GBA
= GND or
G
= DIR = GND
V
IN
= 3.4
V
IN
= GND
FCTxxxT
--
6.0
16.3
(5)
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
FCT2xxxT
--
3.8
13.0
(
5)
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
2634 tbl 09
NOTES:
2634 tbl 10
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. GAB,
GBA
to Bus for 652.
4. This parameter is guaranteed but not tested.
646/648/652T
2646/2652T
646/648/652AT
2646/2652AT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
Bus to Bus
C
L
= 50pF
R
L
= 500
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
t
PZH
t
PZL
Output Enable Time,
G
,
DIR to Bus
(3)
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
ns
t
PHZ
t
PLZ
Output Disable Time,
G
,
DIR to Bus
(3)
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
t
PLH
t
PHL
Propagation Delay
Clock to Bus
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
ns
t
PLH
t
PHL
Propagation Delay SBA or
SAB to Bus
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
ns
t
SU
Set-up Time HIGH or LOW
Bus to Clock
4.0
--
4.5
--
2.0
--
2.0
--
ns
t
H
Hold Time HIGH or LOW
Bus to Clock
2.0
--
2.0
--
1.5
--
1.5
--
ns
t
W
Clock Pulse Width,
HIGH or LOW
6.0
--
6.0
--
5.0
--
5.0
--
ns
646/648/652CT
2646/2652CT
646/652DT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
Bus to Bus
C
L
= 50pF
R
L
= 500
1.5
5.4
1.5
6.0
1.5
4.4
--
--
ns
t
PZH
t
PZL
Output Enable Time,
G
,
DIR to Bus
(3)
1.5
7.8
1.5
8.9
1.5
5.0
--
--
ns
t
PHZ
t
PLZ
Output Disable Time,
G
,
DIR to Bus
(3)
1.5
6.3
1.5
7.7
1.5
4.3
--
--
ns
t
PLH
t
PHL
Propagation Delay
Clock to Bus
1.5
5.7
1.5
6.3
1.5
4.4
--
--
ns
t
PLH
t
PHL
Propagation Delay SBA or
SAB to Bus
1.5
6.2
1.5
7.0
1.5
5.0
--
--
ns
t
SU
Set-up Time HIGH or LOW
Bus to Clock
2.0
--
2.0
--
1.5
--
--
--
ns
t
H
Hold Time HIGH or LOW
Bus to Clock
1.5
--
1.5
--
1.0
--
--
--
ns
t
W
Clock Pulse Width,
HIGH or LOW
(4)
5.0
--
5.0
--
3.0
--
--
--
ns
6.20
8
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
2634 drw 10
2634 drw 11
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2634 drw 12
2634 drw 13
2634 lnk 11
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
2634 drw 14
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
9
ORDERING INFORMATION
IDT XX FCT
XXXX
Device Type
X
Package
X
Process/
Temperature
Range
Blank
B
P
D
SO
L
E
PY
Q
PG
646T
648T
652T
646AT
648AT
652AT
646CT
648CT
652CT
646DT
652DT
Commercial
MIL-STD-883, Class B
Plastic DIP (P24-1)
CERDIP (D24-1)
Small Outline IC (SO24-2)
Leadless Chip Carrier (L28-1)
CERPACK (E24-1)
Shrink Small Outline Package (SO24-7)
Quarter-size Small Outline Package (SO24-8)
Thin Shrink Small Outline Package (SO24-9)
Non-inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Non-inverting Octal Transceiver/Register
2634 drw 15
Temperature
Range
54
74
55
C to +125
C
40
C to +85
C
X
Family
Blank
2
High Drive
Balanced Drive
PDF 
ZIP