Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.10
DSC-4609/2
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
FEATURES:
IDT54/74FCT273 equivalent to FAST
TM
speed;
IDT54/74FCT273A 45% faster than FAST
IDT54/74FCT273C 55% faster than FAST
Equivalent to FAST output drive over full temperature
and voltage supply extremes
I
OL
= 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST
(5
A max.)
Octal D flip-flop with Master Reset
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset (
MR
) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
MR
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FUNCTIONAL BLOCK DIAGRAM
2558 drw 01
D
O
7
CP
Q
D
7
D
O
6
CP
Q
D
6
D
O
5
CP
Q
D
5
D
O
4
CP
Q
D
4
D
O
3
CP
Q
D
3
D
O
2
CP
Q
D
2
D
O
1
CP
Q
D
1
D
O
0
CP
Q
D
0
MR
CP
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
PIN CONFIGURATIONS
5
6
7
8
9
10
D
0
D
1
O
1
1
2
3
4
20
19
18
17
16
15
14
13
Vcc
12
11
MR
D
7
O
2
D
2
D
3
O
3
CP
D
6
O
6
O
5
D
5
D
4
GND
O
4
O
0
O
7
P20-1
D20-1
SO20-2
&
E20-1
2558 drw 02
INDEX
15
14
18
17
16
5
6
7
8
4
L20-2
D
0
D
1
O
1
Vcc
MR
D
7
O
2
D
2
D
3
O
3
CP
D
6
O
6
O
5
D
5
D
4
GND
O
4
O
0
O
7
9 10 11 12 13
3
2
1
20 19
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
1
7.10
2
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
Inputs
Outputs
Operating Mode
MR
MR
CP
D
N
O
N
Reset (Clear)
L
X
X
L
Load "1"
H
h
H
Load "0"
H
l
L
NOTES:
2558 tbl 06
H = HIGH voltage level steady-state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don't care
= LOW-to-HIGH clock transition
PIN DESCRIPTION
Pin Names
Description
D
N
Data Input
MR
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
O
N
Data Outputs
2558 tbl 05
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
V
TERM
(2)
Terminal Voltage
0.5 to +7.0
0.5 to +7.0
V
with Respect
to GND
V
TERM
(3)
Terminal Voltage
0.5 to V
CC
0.5 to V
CC
V
with Respect
to GND
T
A
Operating
0 to +70
55 to +125
C
Temperature
T
BIAS
Temperature
55 to +125
65 to +135
C
Under Bias
T
STG
Storage
55 to +125
65 to +150
C
Temperature
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output Current
120
120
mA
NOTES:
2558 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions Typ. Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
NOTE:
2558 tbl 02
1. This parameter is guaranteed by characterization data and not tested.
7.10
3
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
0.2V
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
V
CC
= Max.
V
I
= V
CC
--
--
5
A
V
I
= 2.7V
--
--
5
(4)
I
IL
Input LOW Current
V
I
= 0.5V
--
--
5
(4)
V
I
= GND
--
--
5
V
IK
Clamp Diode Voltage
Vcc = Min., I
N
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
Vcc = Max.
(3)
, V
O
= GND
60
120
--
mA
V
OH
Output HIGH Voltage
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OH
= 32
A
V
HC
V
CC
--
V
Vcc = Min.
I
OH
= 300
A
V
HC
V
CC
--
V
IN
= V
IH
or V
IL
I
OH
= 12mA MIL.
2.4
4.3
--
I
OH
= 15mA COM'L.
2.4
4.3
--
V
OL
Output LOW Voltage
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
A
--
GND
V
LC
V
Vcc = Min.
I
OL
= 300
A
--
GND
V
LC
(4)
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
--
0.3
0.5
I
OL
= 48mA COM'L.
--
0.3
0.5
NOTES:
2558 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.10
4
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
0.2V
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
Vcc = Max.
--
0.2
1.5
mA
V
IN
V
HC
; V
IN
V
LC
I
CC
Quiescent Power Supply Current
Vcc = Max.
--
0.5
2.0
mA
TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
Vcc = Max.
V
IN
V
HC
--
0.15
0.25
mA/MHz
Outputs Open
V
IN
V
LC
MR
= V
CC
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
Vcc = Max.
V
IN
V
HC
--
1.7
4.0
mA
Outputs Open
V
IN
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
MR
= V
CC
V
IN
= 3.4V
--
2.2
6.0
One Bit Toggling
V
IN
= GND
at f
i
= 5MHz
50% Duty Cycle
Vcc = Max.
V
IN
V
HC
--
4.0
7.8
(5)
Outputs Open
V
IN
V
LC
f
CP
= 10MHz
(FCT)
50% Duty Cycle
MR
= V
CC
V
IN
= 3.4V
--
6.2
16.8
(5)
Eight Bits Toggling
V
IN
= GND
f
i
= 2.5MHz
50% Duty Cycle
NOTES:
2558 tbl 04
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
7.10
5
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Min.
(2)
Max. Min
.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50 pF
2.0
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
5.8
2.0
6.5
ns
t
PHL
Clock to Output
R
L
= 500
t
PHL
Propagation Delay
2.0
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
6.1
2.0
6.8
ns
MR
to Output
t
SU
Set-up Time HIGH
3.0
--
3.5
--
2.0
--
2.0
--
2.0
--
2.0
--
ns
or LOW Data to CP
t
H
Hold Time HIGH
2.0
--
2.0
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
or LOW Data to CP
t
W
Clock Pulse Width
7.0
--
7.0
--
6.0
--
6.0
--
6.0
--
6.0
--
ns
HIGH or LOW
t
W
MR
Pulse Width
7.0
--
7.0
--
6.0
--
6.0
--
6.0
--
6.0
--
ns
LOW
t
REM
Recovery Time
4.0
--
5.0
--
2.0
--
2.5
--
2.0
--
2.5
--
ns
MR
to CP
NOTES:
2558 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
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