IDT54/74FCT299T/AT/CT
Integrated Device Technology, Inc.
DESCRIPTION:
The IDT54/74FCT299T/AT/CT are built using an advanced
dual metal CMOS technology. The IDT54/74FCT299T/AT/
CT are 8-input universal shift/storage registers with 3-state
outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data. The parallel load inputs and
flip-flop outputs are multiplexed to reduce the total number of
package pins. Additional outputs are provided for flip-flops Q
0
and Q
7
to allow easy serial cascading. A separate active LOW
Master Reset is used to reset the register.
FUNCTIONAL BLOCK DIAGRAM
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
1995 Integrated Device Technology, Inc.
6.11
DSC-4205/4
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Std., A and C speed grades
Low input and output leakage
1
A (max.)
CMOS power levels
True TTL input and output compatibility
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit "live insertion"
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
C
D
D
C
P
Q
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
I/O
7
Q
7
DS
7
OE
2
OE
1
MR
Q
0
CP
DS
0
S
1
S
0
2632 drw 01
6.11
2
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LCC
TOP VIEW
5
6
7
8
S
0
OE
1
1
2
3
4
20
19
18
17
16
15
14
13
Vcc
P20-1
D20-1
SO20-2
SO20-8
&
E20-1
OE
2
I/O
6
I/O
4
I/O
2
GND
S
1
DS
7
Q
7
I/O
7
I/O
5
I/O
I/O
1
I/O
0
Q
0
MR
9
10
12
11
3
CP
DS
0
FUNCTION TABLE
(1)
Inputs
MR
MR
S
1
S
0
CP
Response
L
X
X
X
Asynchronous Reset Q
0
Q
7
= LOW
H
H
H
Parallel Load; I/O
n
Q
n
H
L
H
Shift Right; DS
0
Q
0
, Q
0
Q
1
, etc.
H
H
L
Shift Left; DS
7
Q
7
, Q
7
Q
6
, etc.
H
L
L
X
Hold
NOTE:
2632 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH clock transition
PIN DESCRIPTION
Pin Names
Description
CP
Clock Pulse Input (Active Edge Rising)
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
MR
Asynchronous Master Reset Input (Active LOW)
OE
1
,
OE
2
3-State Output Enable Inputs (Active LOW)
I/O
0
I/O
7
Parallel Data Inputs or 3-State Parallel Outputs
O
0
, O
7
Serial Outputs
2632 tbl 01
Symbol
Parameter
(1)
Conditions
Typ.
Max. Unit
C
IN
Input
Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
8
12
pF
2632 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
Symbol
Rating
Commercial
Military
Unit
V
TERM(2)
Terminal Voltage
with Respect to
GND
0.5 to +7.0
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage
with Respect to
GND
0.5 to
V
CC
+0.5
0.5 to
V
CC
+0.5
V
T
A
Operating
Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature
Under Bias
55 to +125
65 to +135
C
T
STG
Storage
Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output
Current
60 to +120 60 to +120 mA
2632 lnk 03
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
2632 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
2632 drw 03
4
5
6
7
8
L20-2
18
17
16
15
14
INDEX
Vcc
GND
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
MR
I/O
1
CP
DS
0
DS
7
Q
7
S
1
S
0
OE
1
OE
2
I/O
7
I/O
5
I/O
3
9 10 11 12 13
3
2
1
20 19
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.11
3
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max., V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max., V
I
= 0.5V
--
--
1
A
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= Vcc (Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
N
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.,
(3)
V
O
= GND
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 6mA MIL.
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 8mA COM'L.
I
OH
= 12mA MIL.
2.0
3.0
--
V
I
OH
= 15mA COM'L.
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 32mA MIL.
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
I
OFF
Input/Output Power Off
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
Leakage
(5)
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power
V
CC
= Max.
--
0.01
1
mA
Supply Current
V
IN
= GND or V
CC
NOTES:
2632 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
5
A at T
A
= -55
C.
5. This parameter is guaranteed but not tested.
6.11
4
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
Vcc = Max.
--
0.5
2.0
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
Vcc = Max.
V
IN
= V
CC
--
0.15
0.25
mA/MHz
Current
(4)
Outputs Open
V
IN
= GND
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
1
= GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
Vcc = Max.
V
IN
= V
CC
--
1.5
3.5
mA
Current
(6)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
V
IN
= 3.4V
--
2.0
5.5
One Bit Toggling
V
IN
= GND
at f
i
= 5MHz
50% Duty Cycle
Vcc = Max.
V
IN
= V
CC
--
3.8
7.3
(5)
Outputs Open
V
IN
= GND
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
V
IN
= 3.4V
--
6.0
16.3
(5)
Eight Bits Toggling
V
IN
= GND
at f
i
= 2.5MHz
50% Duty Cycle
NOTES:
2632 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.11
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299T
IDT54/74FCT299AT
IDT54/74FCT299CT
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Min.
(2)
Max. Min
.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
2.0
10.0
2.0
14.0
2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
t
PHL
CP to Q
0
or Q
7
R
L
= 500
t
PLH
Propagation Delay
2.0
12.0
2.0
12.0
2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
t
PHL
CP to I/O
n
t
PHL
Propagation Delay
2.0
10.0
2.0
10.5
2.0
7.2
2.0
9.5
2.0
6.5
2.0
7.5
ns
MR
to Q
0 or
Q
7
t
PHL
Propagation Delay
2.0
15.0
2.0
15.0
2.0
8.7
2.0
11.5
2.0
6.5
2.0
7.5
ns
MR
to I/O
n
t
PZH
Output Enable Time
1.5
11.0
1.5
15.0
1.5
6.5
1.5
7.5
1.5
6.5
1.5
7.5
ns
t
PZL
OE
n
to I/O
n
t
PHZ
Output Disable Time
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
6.0
1.5
6.5
ns
t
PLZ
OE
n
to I/O
n
t
SU
Set-up Time HIGH
7.5
--
7.5
--
3.5
--
4.0
--
3.5
--
4.0
--
ns
or LOW
S
0 or S
1
to CP
t
SU
Set-up Time HIGH
5.5
--
5.5
--
4.0
--
4.5
--
4.0
--
4.5
--
ns
or LOW I/O
n
,
DS
0
or DS
7
to CP
t
H
Hold Time HIGH
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
ns
or LOW
S
0 or S
1
to CP
t
H
Hold Time HIGH
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
or LOW I/O
n
,
DS
0 or DS
7
to CP
t
W
CP Pulse Width
7.0
--
7.0
--
5.0
--
6.0
--
5.0
--
6.0
--
ns
HIGH or LOW
tw
MR
Pulse Width
7.0
--
7.0
--
5.0
--
6.0
--
5.0
--
6.0
--
ns
LOW
t
REM
Recovery Time
7.0
--
7.0
--
5.0
--
6.0
--
5.0
--
6.0
--
ns
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
NOTES:
2619 tbl 07
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