1
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1999
1999 Integrated Device Technology, Inc.
DSC-2630/5
c
IDT54/74FCT377T/AT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS OCTAL
D FLIP-FLOP WITH
CLOCK ENABLE
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an
advanced dual metal CMOS technology. The IDT54/74FCT377T/AT/CT/
DT have eight edge-triggered, D-type flip-flops with individual D inputs and
O outputs. The common buffered Clock (CP) input loads all flip-flops
simultaneously when the Clock Enable (
CE) is low. The register is fully
edge-triggered. The state of each D input, one set-up time before the low-
to-high clock transition, is transferred to the corresponding flip-flop's O
output. The
CE input must be stable only one set-up time prior to the low-
to-high transition for predictable operation.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
-
Std., A, C and D speed grades
-
Low input and output leakage
1 A (max.)
-
Extended commercial range of 40C to +85C
-
CMOS power levels
-
True TTL input and output compatibility
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
-
High drive outputs (-15mA I
OH
, 48mA I
OL
)
-
Power off disable outputs permit "live insertion"
-
Meets or exceeds JEDEC standard 18 specifications
-
Product available in Radiation Tolerant and Radiation Enhanced
versions
-
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
-
Available in DIP, SOIC, QSOP, CERPACK and LCC packages
CE
CP
D
CP
Q
D
0
O
0
D
CP
Q
D
1
O
1
D
CP
Q
D
2
O
2
D
CP
Q
D
3
O
3
D
CP
Q
D
4
O
4
D
CP
Q
D
5
O
5
D
CP
Q
D
6
O
6
D
CP
Q
D
7
O
7
2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
LCC
TOP VIEW
PIN CONFIGURATION
DIP/ SOIC/ QSOP/ CERPACK
TOP VIEW
1
2
3
4
5
7
9
6
8
10
11
12
13
14
15
16
17
18
19
20
L20-2
O
6
D
7
D
6
O
5
D
5
CE
D
0
O
0
V
CC
O
3
GN
D
CP
O
4
D
4
IN D E X
D
1
O
1
D
3
O
2
D
2
O
7
2
3
1
1 6
1 5
1 4
1 1
1 9
1 8
2 0
1 7
1 3
1 2
5
6
7
4
P20-1
D20-1
SO20-2
SO20-8
E20-1
8
9
1 0
D
1
O
0
D
0
V
CC
O
1
D
3
O
2
D
2
O
3
G ND
O
7
O
6
D
7
D
6
O
5
O
4
D
5
D
4
CP
CE
PIN DESCRIPTION
Pin Names
Description
D
0
D
7
Data Inputs
CE
Clock Enable (Active LOW)
O
0
O
7
Data Outputs
C P
Clock Pulse Input
FUNCTION TABLE
(1)
Inputs
Outputs
Operating Mode
CP
CE
D
O
Load "1"
l
h
H
Load "0"
l
l
L
Hold
h
X
No Change
H
H
X
No Change
NOTE:
1. H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level
l = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
X = Don't Care
= LOW-to-HIGH Clock Transition
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect to GND
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
65 to +120
mA
8T-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (T
A
= +25
O
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
12
pF
8T-link
NOTE:
1. This parameter is measured at characterization but not tested.
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IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 40C to +85C, V
CC
= 5.0V 5%; Military: T
A
= 55C to +125C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
IL
Input LOW Current
(4)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
N
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
O
= GND
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 6mA MIL.
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 8mA COM'L.
I
OH
= 12mA MIL.
2
3
--
V
I
OH
= 15mA COM'L.
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 32mA MIL.
--
0.3
0.5
V
V
IN
= V
IH
or V
IL
I
OL
= 48mA COM'L.
I
OFF
Input/Output Power Off
V
CC
= 0V, V
IN
or V
O
- 4.5V
--
--
1
A
Leakage
(5)
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power
V
CC
= Max.
--
0.01
1
mA
Supply Current
V
IN
= GND or V
CC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is 5
A at T
A
= -55C.
5. This parameter is guaranted but not tested.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply
V
CC
= Max.
--
0.5
2
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
0.15
0.25
mA/
Current
(4)
CE = GND
V
IN
= GND
MHz
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
1.5
3.5
mA
Current
(6)
f
CP
= 10MHz
V
IN
= GND
CE = GND
V
IN
= 3.4V
--
2
5.5
One Bit Toggling
V
IN
= GND
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
--
3.8
7.3
(5)
f
CP
= 10MHz, 50% Duty Cycle
V
IN
= GND
CE = GND
V
IN
= 3.4V
--
6
16.3
(5)
Eight Bits Toggling
V
IN
= GND
f
i
= 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
5
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
IDT54/74FCT377T
FCT54/74FCT377AT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
PLH
t
PHL
Propagation Delay
CP to On
C
L
= 50pF
R
L
= 500
2
13
2
15
2
7.2
2
8.3
ns
t
SU
Set-Up Time HIGH or LOW
Dn to CP
2.5
--
3
--
2
--
2
--
ns
t
H
Hold Time HIGH or LOW
Dn to CP
2
--
2.5
--
1.5
--
1.5
--
ns
t
SU
Set-Up Time HIGH or LOW
CE to CP
4
--
4
--
3.5
--
3.5
--
ns
t
H
Hold Time HIGH or LOW
CE to CP
1.5
--
1.5
--
1.5
--
1.5
--
ns
t
W
Clock Pulse Width,
HIGH or LOW
7
--
7
--
6
--
7
--
ns
IDT54/74FCT377CT
FCT54/74FCT377DT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
PLH
t
PHL
Propagation Delay
CP to On
C
L
= 50pF
R
L
= 500
2
5.2
2
5.5
2
4.4
--
--
ns
t
SU
Set-Up Time HIGH or LOW
Dn to CP
2
--
2
--
2
--
--
--
ns
t
H
Hold Time HIGH or LOW
Dn to CP
1.5
--
1.5
--
1
--
--
--
ns
t
SU
Set-Up Time HIGH or LOW
CE to CP
3.5
--
3.5
--
3
--
--
--
ns
t
H
Hold Time HIGH or LOW
CE to CP
1.5
--
1.5
--
0
--
--
--
ns
t
W
Clock Pulse Width,
HIGH or LOW
6
--
7
--
3
--
--
--
ns
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