MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1995
1995 Integrated Device Technology, Inc.
9.4
DSC-4646/3
Integrated Device Technology, Inc.
1
FAST CMOS
BUFFER/CLOCK DRIVER
FEATURES:
0.5 MICRON CMOS technology
Guaranteed low skew < 600ps (max.)
Very low duty cycle distortion < 700ps (max.)
Low CMOS power levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: 32mA I
OH
, 48mA I
OL
Two independent output banks with 3-state control
One 1:5 Inverting bank
One 1:5 Non-Inverting bank
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Available in DIP, SOIC, SSOP, QSOP, CERPACK and
IDT54/74FCT810BT/CT
LCC packages
Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
3103 drw 02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
OA
1
OA
3
GND
OA
4
OA
5
OA
2
OE
A
IN
A
V
CC
GND
OB
1
OB
2
OB
3
GND
OB
4
GND
IN
B
OB
5
OE
B
V
CC
OE
A
5
IN
A
IN
B
OE
B
OA
1
-OA
5
OB
1
-OB
5
5
3103 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDEX
LCC
TOP VIEW
3
2
20 19
1
4
5
6
7
8
18
17
16
15
14
9 10 11 12 13
L20-2
OA
3
GND
OA
4
OA
5
GND
OB
2
OB
3
GND
OB
4
OB
5
OE
A
IN
A
IN
B
OE
B
GND
OA
2
OA
1
V
CC
V
CC
OB
1
3103 drw 03
PIN CONFIGURATIONS
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
2
PIN DESCRIPTION
3103 tbl 01
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input
Capacitance
V
IN
= 0V
4.5
6.0
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
5.5
8.0
pF
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
V
TERM(2)
Terminal Voltage
with Respect to
GND
0.5 to +7.0
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage
with Respect to
GND
0.5 to V
CC
+0.5
0.5 to V
CC
+0.5
V
T
A
Operating
Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature
Under Bias
55 to +125
65 to +135
C
T
STG
Storage
Temperature
55 to +125
65 to +150
C
I
OUT
DC Output
Current
60 to +120
60 to +120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals.
3. Output and I/O terminals.
3103 lnk 03
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
5
A at T
A
= 55
C.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current
(5)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
I L
Input LOW Current
(5)
V
CC
= Max.
V
I
= 0.5V
--
--
1
A
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
A
I
I
Input HIGH Current
(5)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
O
= GND
60
120
225
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.4
3.3
--
V
I
OH
= 24mA MIL.
I
OH
= 32mA COM'L.
(4)
2.0
3.0
--
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
--
0.3
0.55
V
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
V
H
Input Hysteresis for all inputs
--
--
150
--
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
5
500
A
3103 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
3103 lnk 02
Pin Names
Description
OE
A
,
OE
B
3-State Output Enable Inputs (Active LOW)
IN
A
, IN
B
Clock Inputs
OA
n
,
OB
n
Clock Outputs
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
3
POWER SUPPLY CHARACTERISTICS
3103 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input; (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and
I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
60
100
A/
MHz/bit
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fo= 25MHz
V
IN
= V
CC
V
IN
= GND
--
7.5
13
mA
50% Duty Cycle
OE
A
= GND,
OE
B
=V
CC
V
IN
= 3.4V
V
IN
= GND
--
7.8
14.0
V
CC
= Max.
Outputs Open
fo = 50MHz
V
IN
= V
CC
V
IN
= GND
--
30.0
50.5
(5)
50% Duty Cycle
OE
A
=
OE
B
= GND
V
IN
= 3.4V
V
IN
= GND
--
30.5
52.5
(5)
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
4
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay
limits do not imply skew.
3103 tbl 06
IDT54/74FCT810BT
IDT54/74FCT810CT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Min
.(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
IN
A
to OA
n
, IN
B
to
OB
n
C
L
= 50pF
R
L
= 500
1.5
4.5
1.5
4.9
1.5
4.3
1.5
4.6
ns
t
R
Output Rise Time
--
1.5
--
2.0
--
1.5
--
2.0
ns
t
F
Output Fall Time
--
1.5
--
1.5
--
1.5
--
1.5
ns
t
SK1
(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
--
0.5
--
0.9
--
0.3
--
0.7
ns
t
SK2
(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
--
0.7
--
1.1
--
0.6
--
1.0
ns
t
SK
(p)
Pulse skew: skew between opposite
transitions of same output |(t
PHL
-t
PLH
)|
--
0.7
--
1.2
--
0.7
--
1.1
ns
t
SK
(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
--
1.2
--
1.5
--
1.0
--
1.2
ns
t
PZL
t
PZH
Output Enable Time
OE
A
to OA
n
,
OE
B
to
OB
n
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
t
PLZ
t
PHZ
Output Disable Time
OE
A
to OA
n
,
OE
B
to
OB
n
1.5
6.0
1.5
6.5
1.5
5.0
1.5
6.0
ns
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
5
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f
1.0MHz; t
F
2.5ns; t
R
2.5ns
Package 1 and Package 2 are same device type and speed grade
3103 drw 10
3103 drw 09
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
t
PD1a
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
t
SK2(o)
t
PD2a
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT
t
PD1b
t
PD2b
t
SK2(o)
t
SK(t)
=
|t
PD2a -
t
PD1a
|
or
|t
PD2b-
t
PD1b
|
PACKAGE SKEW - t
SK
(t)
ENABLE AND DISABLE TIMES
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
ENABLE AND DISABLE TIME
SWITCH POSITION
Test
Switch
Disable LOW
Enable LOW
Closed
Disable HIGH
Enable HIGH
Open
3103 lnk 07
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3103 drw 04
3103 drw 07
3103 drw 08
t
PLH
t
PHL
3V
0V
V
OH
1.5V
1.5V
V
OL
t
SK(p)
=
|t
PHL -
t
PLH
|
INPUT
OUTPUT
t
PLH1
OUTPUT 1
OUTPUT 2
t
SK2(o)
t
PHL2
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT
t
PHL1
t
PLH2
t
SK2(o)
t
SK2(o)
=
|t
PHL2 -
t
PLH1
|
or
|t
PLH2 -
t
PHL1
|
3103 drw 06
3103 drw 05
TEST WAVEFORMS
PACKAGE DELAY
3V
0V
V
OH
t
PLH
t
PHL
V
OL
1.5V
1.5V
t
R
t
F
2.0V
0.8V
t
PLH1
OUTPUT 1
OUTPUT 2
t
SK1(o)
t
PLH2
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT
t
PHL1
t
PHL2
t
SK1(o)
t
SK1(o)
=
|t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PLH1
|
INPUT
OUTPUT
OUTPUT SKEW (ALL BANKS) - t
SK2
(o)
PULSE SKEW - t
SK
(p)
OUTPUT SKEW (SAME BANK) - t
SK1
(o)
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4
6
ORDERING INFORMATION
XXX
Device Type
XX
Package
X
Process/
Blank
B
P
D
E
L
SO
PY
Q
810BT
810CT
Commercial
Military (-55
C to +125
C) Compliant to
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
Temperature
Range
IDTXXFCT
Temp. Range
54
74
-55
C to +125
C
0
C to + 70
C
Inverting, Non-Inverting Buffer/Clock driver
3103 drw 13
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