IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
1
Integrated Device Technology, Inc.
1
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT54/74FCT821AT/BT/CT
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
FEATURES:
Common features:
Low input and output leakage
1
A (max.)
CMOS power levels
True TTL input and output compatibility
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
Features for FCT821T/FCT823T/FCT825T:
A, B, C and D speed grades
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit "live insertion"
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (
EN
) and Clear (
CLR
) ideal for parity bus
interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (
OE
1,
OE
2,
OE
3) to allow multi-
user control of the interface, e.g.,
CS
, DMA and RD/
WR
. They
are ideal for use as an output port requiring high I
OL
/I
OH
.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc
6.21
DSC-4202/5
FUNCTIONAL BLOCK DIAGRAM
D
CP Q
Q
CL
D
CP Q
Q
CL
D
0
D
N
Y
0
Y
N
EN
CLR
CP
OE
2567 drw 01
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
2
PIN CONFIGURATIONS
FCT821 10-BIT REGISTER
2567 drw 04
2567 drw 03
FCT823 9-BIT REGISTER
2567 drw 02
INDEX
D
2
Y
2
Y
3
Y
4
NC
Y
5
OE
D
1
NC
V
CC
Y
0
D
8
GND
CP
Y
9
Y
8
LCC
TOP VIEW
3 2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
1213
L28-1
D
3
D
4
NC
D
5
D
6
D
7
D
0
Y
1
Y
6
Y
7
21
22
23
24
25
26
27
28
D
9
NC
INDEX
D
2
Y
2
Y
3
Y
4
NC
Y
5
OE
D
1
NC
V
CC
Y
0
LCC
TOP VIEW
3 2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
1213
L28-1
D
3
D
4
NC
D
5
D
6
D
7
D
8
GND
CP
EN
Y
8
D
0
Y
1
Y
6
Y
7
21
22
23
24
25
26
27
28
CLR
NC
INDEX
D
1
Y
1
Y
2
Y
3
NC
Y
4
D
0
NC
V
CC
OE
3
LCC
TOP VIEW
3 2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
1213
L28-1
D
2
D
3
NC
D
4
D
5
D
6
D
7
GND
CP
EN
Y
7
OE
2
Y
0
Y
5
Y
6
21
22
23
24
25
26
27
28
CLR
NC
OE
1
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
6
CP
Y
5
Y
7
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
E24-1
11
12
21
22
23
24
D
8
CLR
Y
8
EN
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
6
CP
Y
5
Y
7
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
E24-1
11
12
21
22
23
24
D
8
D
9
Y
8
Y
9
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
FCT825 8-BIT REGISTER
OE
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
6
CP
Y
5
Y
7
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-8
&
E24-1
11
12
21
22
23
24
DIP/SOIC/QSOP/CERPACK
TOP VIEW
OE
2
CLR
OE
3
EN
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
3
FUNCTION TABLE
(1)
PIN DESCRIPTION
2567 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE (
T
A
= +25
C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
V
TERM(2)
Terminal Voltage
with Respect to
GND
0.5 to +7.0
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage
with Respect to
GND
0.5 to
V
CC
+0.5
0.5 to
V
CC
+0.5
V
T
A
Operating
Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature
Under Bias
55 to +125
65 to +135
C
T
STG
Storage
Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output
Current
60 to +120 60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
NOTE:
1. This parameter is measured at characterization but not tested.
2567 lnk 03
2567 lnk 04
Symbol
Parameter
(1)
Conditions
Typ.
Max. Unit
C
IN
Input
Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
8
12
pF
Inputs
Internal/
Outputs
OE
OE
CLR
CLR
EN
EN
D
I
CP
Q
I
Y
I
Function
H
H
H
H
L
L
L
H
L
H
Z
Z
High Z
H
L
L
L
X
X
X
X
X
X
L
L
Z
L
Clear
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
Hold
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
L
H
L
H
Z
Z
L
H
Load
Names
I/O
Description
D
I
I
The D flip-flop data inputs.
CLR
I
When the clear input is LOW and
OE
is
LOW, the Q
I
outputs are LOW. When
the clear input is HIGH, data can be
entered into the register.
CP
I
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
Y
I
O
The register 3-state outputs.
EN
I
Clock Enable. When the clock enable is
LOW, data on the D
I
input is transferred
to the Q
I
output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change
state, regardless of the data or clock
input transitions.
OE
I
Output Control. When the
OE
input is
HIGH, the Y
I
outputs are in the high-
impedance state. When the
OE
input is
LOW, the TRUE register data is present
at the Y
I
outputs.
NOTE:
2567 tbl 02
1. H = HIGH
L = LOW
X = Don't Care
NC = No Change
= LOW-to-HIGH Transition
Z = High Impedance
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
4
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
I L
Input LOW Current
(4)
V
I
= 0.5V
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
2567 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 6mA MIL.
I
OH
= 8mA COM'L.
2.4
3.3
--
V
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.0
3.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
--
0.3
0.5
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
2567 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
5
A at T
A
= 55
C.
5. This parameter is guaranteed but not tested.
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
5
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
0.15
0.25
mA/
MHz
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
1.5
3.5
mA
OE
=
EN
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
IN
= 3.4V
V
IN
= GND
--
2.0
5.5
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
3.8
7.3
(5)
OE
=
EN
= GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
V
IN
= 3.4V
V
IN
= GND
--
6.0
16.3
(5)
2567 tbl 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
6
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT
FCT821/823/825BT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
CP to Y
I
(
OE
= LOW)
C
L
= 50pF
R
L
= 500
1.5
10.0
1.5
11.5
1.5
7.5
1.5
8.5
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
20.0
1.5
20.0
1.5
15.0
1.5
16.0
t
SU
Set-up Time HIGH or LOW
D
I
to CP
C
L
= 50pF
R
L
= 500
4.0
--
4.0
--
3.0
--
3.0
--
ns
t
H
Hold Time HIGH or LOW
D
I
to CP
2.0
--
2.0
--
1.5
--
1.5
--
ns
t
SU
Set-up Time HIGH or LOW
EN
to CP
4.0
--
4.0
--
3.0
--
3.0
--
ns
t
H
Hold Time HIGH or LOW
EN
to CP
2.0
--
2.0
--
0
--
0
--
ns
t
PHL
Propagation Delay,
CLR
to Y
I
1.5
14.0
1.5
15.0
1.5
9.0
1.5
9.5
ns
t
REM
Recovery Time
CLR
to CP
6.0
--
7.0
--
6.0
--
6.0
--
ns
t
W
Clock Pulse Width
HIGH or LOW
7.0
--
7.0
--
6.0
--
6.0
--
ns
t
W
CLR
Pulse Width LOW
6.0
--
7.0
--
6.0
--
6.0
--
ns
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
1.5
12.0
1.5
13.0
1.5
8.0
1.5
9.0
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
23.0
1.5
25.0
1.5
15.0
1.5
16.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 5pF
(4)
R
L
= 500
1.5
7.0
1.5
8.0
1.5
6.5
1.5
7.0
ns
C
L
= 50pF
R
L
= 500
1.5
8.0
1.5
9.0
1.5
7.5
1.5
8.0
NOTES:
2567 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825CT
FCT823DT
Com'l.
Mil.
Com'l.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max.
Min
.
(2)
Max.
Min
.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
CP to Y
I
(
OE
= LOW)
C
L
= 50pF
R
L
= 500
1.5
6.0
1.5
7.0
1.5
5.0
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
12.5
1.5
13.5
1.5
8.5
t
SU
Set-up Time HIGH or LOW
D
I
to CP
C
L
= 50pF
R
L
= 500
3.0
--
3.0
--
2.0
--
ns
t
H
Hold Time HIGH or LOW
D
I
to CP
1.5
--
1.5
--
1.0
--
ns
t
SU
Set-up Time HIGH or LOW
EN
to CP
3.0
--
3.0
--
3.0
--
ns
t
H
Hold Time HIGH or LOW
EN
to CP
0
--
0
--
0
--
ns
t
PHL
Propagation Delay,
CLR
to Y
I
1.5
8.0
1.5
8.5
1.5
5.0
ns
t
REM
Recovery Time
CLR
to CP
6.0
--
6.0
--
3.0
--
ns
t
W
Clock Pulse Width
HIGH or LOW
(3)
6.0
--
6.0
--
3.0
--
ns
t
W
CLR
Pulse Width LOW
(3)
6.0
--
6.0
--
3.0
--
ns
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
1.5
7.0
1.5
8.0
1.5
4.8
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
12.5
1.5
13.5
1.5
9.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 5pF
(4)
R
L
= 500
1.5
6.0
1.5
6.0
1.5
4.0
ns
C
L
= 50pF
R
L
= 500
1.5
6.5
1.5
6.5
1.5
4.0
NOTES:
2567 tbl 09
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
8
PULSE WIDTH
SWITCH POSITION
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2567 drw 05
2567 drw 06
2567 drw 07
2567 drw 08
2567 drw 09
2567 lnk 10
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
9
ORDERING INFORMATION
XX
Temp. Range
XXXX
Device Type
X
Package
X
Process
Blank
B
P
D
E
L
SO
PY
Q
821AT
823AT
825AT
821BT
823BT
825BT
821CT
823CT
825CT
823DT
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
8-Bit Non-Inverting Register
54
74
55
C to +125
C
0
C to +70
C
IDT
2567 drw 10
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