Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1994
1994 Integrated Device Technology, Inc.
7.22
DSC-4603/2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
FEATURES:
Equivalent to AMD's Am29841-46 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
IDT54/74FCT841A equivalent to FAST
TM
speed
IDT54/74FCT841B 25% faster than FAST
IDT54/74FCT841C 40% faster than FAST
Buffered common latch enable, clear and preset inputs
I
OL
= 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than AMD's
bipolar Am29800 series (5
A max.)
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular `373 function.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-imped-
ance state.
1
2607 drw 01
FUNCTIONAL BLOCK DIAGRAM
D
0
D
CLR
Y
0
LE Q
P
CLR
LE
OE
PRE
D
N
D
CLR
Y
N
LE Q
P
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
7.22
2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
6
LE
Y
5
Y
7
V
CC
P24-1
D24-1
E24-1
&
SO24-2
D
8
D
9
Y
8
Y
9
DIP/CERPACK/SOIC
TOP VIEW
INDEX
D
2
Y
2
Y
3
Y
4
NC
Y
5
OE
D
1
NC
V
CC
Y
0
D
8
GND
LE
Y
9
Y
8
LCC
TOP VIEW
L28-1
D
3
D
4
NC
D
5
D
6
D
7
D
0
Y
1
Y
6
Y
7
D
9
NC
3
2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
12 13
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
11
12
21
22
23
24
2607 drw 02
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE
(1)
Name
I/O
Description
CLR
I
When
CLR
is LOW, the outputs are
LOW if
OE
is LOW. When
CLR
is HIGH,
data can be entered into the latch.
D
I
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
Y
I
O
The 3-state latch outputs.
OE
I
The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs (Y
I
) are in the
high-impedance (off) state.
PRE
I
Preset line. When
PRE
is LOW, the
outputs are HIGH if
OE
is LOW. Preset
overrides
CLR
.
2607 tbl 01
Inputs
Inter-
nal
Out-
puts
CLR
CLR PRE
PRE OE
OE
LE
D
I
Q
I
Y
I
Function
H
H
H
X
X
X
Z
High Z
H
H
H
H
L
L
Z
High Z
H
H
H
H
H
H
Z
High Z
H
H
H
L
X
NC
Z
Latched (High Z)
H
H
L
H
L
L
L
Transparent
H
H
L
H
H
H
H
Transparent
H
H
L
L
X
NC
NC
Latched
H
L
L
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched (High Z)
H
L
H
L
X
H
Z
Latched (High Z)
NOTE:
2607 tbl 02
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change,
Z = High Impedance
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22
3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
V
TERM(2)
Terminal Voltage
with Respect to
GND
0.5 to +7.0
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage
with Respect to
GND
0.5 to V
CC
0.5 to V
CC
V
T
A
Operating
Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature
Under Bias
55 to +125
65 to +135
C
T
STG
Storage
Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output
Current
120
120
mA
NOTE:
2607 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input
Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
8
12
pF
NOTE:
2607 tbl 04
1. This parameter is measured at characterization but not tested.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
0.2V
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
NOTES:
2607 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current
V
CC
= Max.
V
I
= V
CC
--
--
5
A
V
I
= 2.7V
--
--
5
(4)
I
I L
Input LOW Current
V
I
= 0.5V
--
--
5
(4)
V
I
= GND
--
--
5
I
OZH
Off State (High Impedance)
V
CC
= Max.
V
O
= V
CC
--
--
10
A
Output Current
V
O
= 2.7V
--
--
10
(4)
I
OZL
V
O
= 0.5V
--
--
10
(4)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= Min., I
N
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max.
(3)
, V
O
= GND
75
120
--
mA
V
OH
Output HIGH Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= 32
A
V
HC
V
CC
--
V
V
CC
= Min.
I
OH
= 300
A
V
HC
V
CC
--
V
IN
= V
IH
or V
IL
I
OH
= 15mA MIL.
2.4
4.3
--
I
OH
= 24mA COM'L.
2.4
4.3
--
V
OL
Output LOW Voltage
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
A
--
GND
V
LC
V
V
CC
= Min.
I
OL
= 300
A
--
GND
V
LC(4)
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
--
0.3
0.5
I
OL
= 48mA COM'L.
--
0.3
0.5
7.22
4
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
0.2V
NOTES:
2607 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VC
C
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max.
V
IN
V
HC
; V
IN
V
LC
--
0.2
1.5
mA
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
2.0
mA
I
CCD
Dynamic Power Supply
Current
(4)
V
CC
= Max.
Outputs Open
OE
= GND
LE = V
CC
One Input Toggling
50% Duty Cycle
V
IN
V
HC
V
IN
V
LC
--
0.15
0.25
mA/
MHz
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
V
IN
V
HC
V
IN
V
LC
(FCT)
--
1.7
4.0
mA
OE
= GND
LE = V
CC
One Bit Toggling
V
IN
= 3.4V
V
IN
= GND
--
2.0
5.0
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
V
IN
V
HC
V
IN
V
LC
(FCT)
--
3.2
6.5
(5)
OE
= GND
LE = V
CC
Eight Bits Toggling
V
IN
= 3.4V
V
IN
= GND
--
5.2
14.5
(5)
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A
FCT841B
FCT841C
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
D
I
to
Y
I
(LE = HIGH)
C
L
= 50pF
R
L
= 500
1.5
9.0
1.5
10.0 1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
13.0 1.5
15.0 1.5
13.0 1.5
15.0 1.5
13.0 1.5
15.0
t
PLH
t
PHL
Propagation Delay
LE to Y
I
C
L
= 50pF
R
L
= 500
1.5
12.0 1.5
13.0 1.5
8.0
1.5
10.5 1.5
6.4
1.5
6.8
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
16.0 1.5
20.0 1.5
15.5 1.5
18.0 1.5
15.0 1.5
16.0
t
PLH
Propagation Delay,
PRE
to Y
I
C
L
= 50pF
1.5
12.0 1.5
14.0 1.5
8.0
1.5
10.0 1.5
7.0
1.5
9.0
ns
t
PHL
R
L
= 500
1.5
14.0 1.5
17.0 1.5
10.0 1.5
13.0 1.5
9.0
1.5
12.0
t
PHL
Propagation Delay,
CLR
to Y
I
1.5
13.0 1.5
14.0 1.5
10.0 1.5
11.0 1.5
9.0
1.5
10.0
ns
t
PLH
1.5
14.0 1.5
17.0 1.5
10.0 1.5
10.0 1.5
9.0
1.5
9.0
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
1.5
11.5 1.5
13.0 1.5
8.0
1.5
8.5
1.5
6.5
1.5
7.3
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
23.0 1.5
25.0 1.5
14.0 1.5
15.0 1.5
12.0 1.5
13.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 5pF
(4)
R
L
= 500
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
5.7
1.5
6.0
ns
C
L
= 50pF
R
L
= 500
1.5
8.0
1.5
10.0 1.5
7.0
1.5
7.5
1.5
6.0
1.5
6.3
t
SU
Data to LE Set-up Time
C
L
= 50pF
2.5
--
2.5
--
2.5
--
2.5
--
2.5
--
2.5
--
ns
t
H
Data to LE Hold Time
R
L
= 500
2.5
--
3.0
--
2.5
--
2.5
--
2.5
--
2.5
--
ns
t
W
LE Pulse Width
(3)
HIGH
4.0
--
5.0
--
4.0
--
4.0
--
4.0
--
4.0
--
ns
t
W
PRE
Pulse Width
(3)
LOW
5.0
--
7.0
--
4.0
--
4.0
--
4.0
--
4.0
--
ns
t
W
CLR
Pulse Width
(3)
LOW
4.0
--
5.0
--
4.0
--
4.0
--
4.0
--
4.0
--
ns
t
REM
Recovery Time
PRE
to LE
4.0
--
4.0
--
4.0
--
4.0
--
4.0
--
4.0
--
ns
t
REM
Recovery Time
CLR
to LE
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
3.0
--
ns
NOTES:
2607 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
7.22
6
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2607 tbl 08
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
2607 drw 04
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22
7
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device Type
X
Package
X
Process
Blank
B
P
D
E
L
SO
841A
841B
841C
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
10-Bit Non-Inverting Latch
54
74
55
C to +125
C
0
C to +70
C
FCT
2607 drw 05
PDF 
ZIP