Integrated Device Technology, Inc.
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST CMOS
BUS INTERFACE
LATCHES
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
The FCT8xxT bus interface latches are designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high I
OL
/I
OH
.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capaci-
tance bus loading in high-impedance state.
FEATURES:
Common features:
Low input and output leakage
1
A (max.)
CMOS power levels
True TTL input and output compatibility
V
OH
= 3.3V (typ.)
V
OL
= 0.3V (typ.)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
Features for FCT841T:
A, B, C and D speed grades
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit "live insertion"
IDT54/74FCT841AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 1996
1996 Integrated Device Technology, Inc.
6.22
2571/6
FUNCTIONAL BLOCK DIAGRAM
D
0
D
Y
0
LE Q
LE
OE
D
1
D
Y
1
LE Q
D
2
D
Y
2
LE Q
D
3
D
Y
3
LE Q
D
4
D
Y
4
LE Q
D
5
D
Y
5
LE Q
D
8
D
Y
8
LE Q
D
9
D
Y
9
LE Q
2571 drw 01
6.22
2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
2571 drw 02
2571 drw 03
INDEX
D
2
Y
2
Y
3
Y
4
NC
Y
5
OE
D
1
NC
V
CC
Y
0
D
8
GND
LE
Y
9
Y
8
LCC
TOP VIEW
3 2
20
19
1
4
5
6
7
8
18
17
16
15
14
9
10
11
1213
L28-1
D
3
D
4
NC
D
5
D
6
D
7
D
0
Y
1
Y
6
Y
7
21
22
23
24
25
26
27
28
D
9
NC
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Y
0
Y
1
Y
2
Y
3
Y
4
Y
6
LE
Y
5
Y
7
V
CC
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
E24-1
11
12
21
22
23
24
D
8
D
9
Y
8
Y
9
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE
(1)
2571 tbl 01
NOTE:
2571 tbl 02
1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
V
TERM(2)
Terminal Voltage
with Respect to
GND
0.5 to +7.0
0.5 to +7.0
V
V
TERM(3)
Terminal Voltage
with Respect to
GND
0.5 to
V
CC
+0.5
0.5 to
V
CC
+0.5
V
T
A
Operating
Temperature
0 to +70
55 to +125
C
T
BIAS
Temperature
Under Bias
55 to +125
65 to +135
C
T
STG
Storage
Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
0.5
0.5
W
I
OUT
DC Output
Current
60 to +120 60 to +120 mA
2571 lnk 03
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
2571 lnk 04
Symbol
Parameter
(1)
Conditions
Typ.
Max. Unit
C
IN
Input
Capacitance
V
IN
= 0V
6
10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
8
12
pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
Name
I/O
Description
D
I
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
Y
I
O
The 3-state latch outputs.
OE
I
The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs VI
are in high-
impedance (off) state.
Inputs
Internal Output
OE
OE
LE
D
I
Q
I
Y
I
Function
H
H
L
L
Z
High Z
H
H
H
H
Z
High Z
H
L
X
NC
Z
Latched (High Z)
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Latched
6.22
3
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0
C to +70
C, V
CC
= 5.0V
5%; Military: T
A
= 55
C to +125
C, V
CC
= 5.0V
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
I H
Input HIGH Current
(4)
V
CC
= Max.
V
I
= 2.7V
--
--
1
A
I
I L
Input LOW Current
(4)
V
I
= 0.5V
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(4)
V
O
= 0.5V
--
--
1
I
I
Input HIGH Current
(4)
V
CC
= Max., V
I
= V
CC
(Max.)
--
--
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
--
--
200
--
mV
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
--
0.01
1
mA
2571 lnk 05
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= 6mA MIL.
I
OH
= 8mA COM'L.
2.4
3.3
--
V
I
OH
= 12mA MIL.
I
OH
= 15mA COM'L.
2.0
3.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
--
0.3
0.5
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
60
120
225
mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
4.5V
--
--
1
A
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
2571 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
5
A at T
A
= 55
C.
5. This parameter is guaranteed but not tested.
6.22
4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
OE
= GND
V
IN
= V
CC
V
IN
= GND
--
0.15
0.25
mA/
MHz
LE = V
CC
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
--
1.5
3.5
mA
Outputs Open
fi = 10MHz
V
IN
= GND
50% Duty Cycle
OE
=
GND
V
IN
= 3.4
V
IN
= GND
--
1.8
4.5
LE = V
CC
One Bit Toggling
V
CC
= Max.
V
IN
= V
CC
--
3.0
6.0
(5)
Outputs Open
fi = 2.5MHz
V
IN
= GND
50% Duty Cycle
OE
=
GND
V
IN
= 3.4
V
IN
= GND
--
5.0
14.0
(5)
LE = V
CC
Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2571 tbl 07
6.22
5
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT
FCT841BT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Conditions
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
D
I
to Y
I
(LE = HIGH)
C
L
= 50pF
R
L
= 500
1.5
9.0
1.5
10.0
1.5
6.5
1.5
7.5
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
13.0
1.5
15.0
1.5
13.0
1.5
15.0
t
PLH
t
PHL
Propagation Delay
LE to Y
I
C
L
= 50pF
R
L
= 500
1.5
12.0
1.5
13.0
1.5
8.0
1.5
10.5
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
16.0
1.5
20.0
1.5
15.5
1.5
18.0
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
1.5
11.5
1.5
13.0
1.5
8.0
1.5
8.5
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
23.0
1.5
25.0
1.5
14.0
1.5
15.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 5pF
(4)
R
L
= 500
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
ns
C
L
= 50pF
R
L
= 500
1.5
8.0
1.5
10.0
1.5
7.0
1.5
7.5
t
SU
Data to LE Set-up Time
C
L
= 50pF
2.5
--
2.5
--
2.5
--
2.5
--
ns
t
H
Data to LE Hold Time
R
L
= 500
2.5
--
3.0
--
2.5
--
2.5
--
ns
t
W
LE Pulse Width HIGH
(3)
4.0
--
5.0
--
4.0
--
4.0
--
ns
NOTES:
2571 tbl 08
1. See test circuit and waveforms.
3. These parameters are guaranteed but not tested.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4. These conditions are guaranteed but not tested.
FCT841CT
FCT841DT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Conditions
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
t
PHL
Propagation Delay
D
I
to Y
I
(LE = HIGH)
C
L
= 50pF
R
L
= 500
1.5
5.5
1.5
6.3
1.5
4.2
--
--
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
13.0
1.5
15.0
1.5
8.0
--
--
t
PLH
t
PHL
Propagation Delay
LE to Y
I
C
L
= 50pF
R
L
= 500
1.5
6.4
1.5
6.8
1.5
4.0
--
--
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
15.0
1.5
16.0
1.5
8.0
--
--
t
PZH
t
PZL
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
1.5
6.5
1.5
7.3
1.5
4.8
--
--
ns
C
L
= 300pF
(4)
R
L
= 500
1.5
12.0
1.5
13.0
1.5
9.0
--
--
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 5pF
(4)
R
L
= 500
1.5
5.7
1.5
6.0
1.5
4.0
--
--
ns
C
L
= 50pF
R
L
= 500
1.5
6.0
1.5
6.3
1.5
4.0
--
--
t
SU
Data to LE Set-up Time
C
L
= 50pF
2.5
--
2.5
--
1.5
--
--
--
ns
t
H
Data to LE Hold Time
R
L
= 500
2.5
--
2.5
--
1.0
--
--
--
ns
t
W
LE Pulse Width HIGH
(3)
4.0
--
4.0
--
3.0
--
--
--
ns
NOTES:
2571 tbl 09
1. See test circuit and waveforms.
3. These parameters are guaranteed but not tested.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4. These conditions are guaranteed but not tested.
6.22
6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2571 drw 04
2571 drw 05
2571 drw 06
2571 drw 07
2571 lnk 11
2571 drw 08
6.22
7
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2571 drw 09
IDT XX
Temp. Range
XXXX
Device Type
X
Package
X
Process
Blank
B
P
D
E
L
SO
PY
Q
841AT
841BT
841CT
841DT
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
10-Bit Non-Inverting Latch
54
74
55
C to +125
C
0
C to +70
C
FCT
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