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Электронный компонент: IDT7005L25PF

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Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
1996 Integrated Device Technology, Inc.
DSC-2738/6
IDT7005S/L
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
FEATURES:
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
High-speed access
-- Military: 20/25/35/55/70ns (max.)
-- Commercial:15/17/20/25/35/55ns (max.)
Low-power operation
-- IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
-- IDT7005L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of Semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation--2V data retention
TTL-compatible, single 5V (
10%) power supply
Available in 68-pin PGA, 68-pin quad flatpack, 68-pin
PLCC, and a 64-pin TQFP
Industrial temperature range (40
C to +85
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.
The IDT7005 is designed to be used as a stand-alone Dual-
Port RAM or as a combination MASTER/SLAVE Dual-Port
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
12L
A
0L
2738 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/
W
L
SEM
L
INT
L
M/
S
BUSY
R
I/O
0R
-I/O
7R
A
12R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
R/
W
R
13
13
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.06
6.06
2
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RAM for 16-bit-or-more word systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT's CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500
W from a 2V
battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, a 68-
pin quad flatpack, a 68-pin PLCC and a 64-pin Thin Plastic
Quad Flatpack (TQFP). Military grade product is manufac-
tured in compliance with the latest revision of MIL-STD-883,
Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
PIN CONFIGURATIONS
(1,2)
2738 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
9
8
7
6
5
4
3
2
1 68 67 66 65
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
V
CC
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
GND
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R/
W
L
11
10
M/
S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
GND
I/O
0R
V
CC
A
4R
BUSY
L
GND
BUSY
R
INT
R
A
12R
I/O
7R
N/C
GND
OE
R
R/
W
R
SEM
R
CE
R
OE
L
SEM
L
CE
L
N/C
I/O
0L
I/O
1L
IDT7005
J68-1
F68-1
PLCC / FLATPACK
TOP VIEW
(3)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N/C
A
12L
N/C
A
11R
N/C
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the the actual part-marking.
INDEX
IDT7005
PN-64
TQFP
TOP VIEW
(3)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
GND
M/
S
OE
L
A
5L
I/O
1L
R/
W
L
CE
L
SEM
L
V
CC
N/C
N/C
OE
R
CE
R
R/
W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2738 drw 03
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
3
Left Port
Right Port
Names
CE
L
CE
R
Chip Enable
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
A
12L
A
0R
A
12R
Address
I/O
0L
I/O
7L
I/O
0R
I/O
7R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/
S
Master or Slave Select
V
CC
Power
GND
Ground
PIN NAMES
2738 tbl 01
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate oriention of the actual part-marking
PIN CONFIGURATIONS (CON'T.)
(1,2)
2738 drw 04
51
50
48
46
44
42
40
38
36
53
55
57
59
61
63
65
67
68
66
1
3
5
7
9
11
13
15
20
22
24
26
28
30
32
35
IDT7005
G68-1
68-PIN PGA
TOP VIEW(3)
A
B
C
D
E
F
G
H
J
K
L
47
45
43
41
34
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49
39
37
A
5L
INT
L
N/C
SEM
L
CE
L
V
CC
OE
L
R/
W
L
I/O
0L
N/C
GND
GND
I/O
0R
V
CC
N/C
OE
R
R/
W
R
SEM
R
CE
R
GND
BUSY
R
BUSY
L
M/
S
INT
R
N/C
GND
A
1R
N/C
N/C
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
6.06
4
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
CE
CE
CE
CE
R/
W
W
W
W
W
OE
OE
OE
OE
OE
SEM
SEM
SEM
SEM
SEM
I/O
0-7
Mode
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to Memory
L
H
L
H
DATA
OUT
Read Memory
X
X
H
X
High-Z
Outputs Disabled
NOTE:
2738 tbl 02
1. A
0L
-- A
12L
is not equal to A
0R
-- A
12R.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
2.2
--
6.0
(2)
V
V
IL
Input Low Voltage
0.5
(1)
--
0.8
V
NOTES:
2738 tbl 06
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade
Temperature
GND
V
CC
Military
55
C to +125
C
0V
5.0V
10%
Commercial
0
C to +70
C
0V
5.0V
10%
2738 tbl 05
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
V
TERM
(2)
Terminal Voltage 0.5 to +7.0
0.5 to +7.0
V
with Respect
to GND
T
A
Operating
0 to +70
55 to +125
C
Temperature
T
BIAS
Temperature
55 to +125
65 to +135
C
Under Bias
T
STG
Storage
55 to +125
65 to +150
C
Temperature
I
OUT
DC Output
50
50
mA
Current
NOTES:
2738 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10% maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
CAPACITANCE
(1)
(T
A
= +25
C, f = 1.0MHz) TQFP PACKAGE
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output
V
OUT
= 3dV
10
pF
Capacitance
NOTES:
2738 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
TRUTH TABLE II SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
CE
CE
CE
CE
R/
W
W
W
W
W
OE
OE
OE
OE
OE
SEM
SEM
SEM
SEM
SEM
I/O
0-7
Mode
H
H
L
L
DATA
OUT
Read in Semaphore Flag Data 0ut
H
u
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
--
Not Allowed
2738 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0 -
I/O
15
. These eight semaphores are addressed by A
0
- A
2.
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
5
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 5.0V
10%)
7005X15
7005X17
7005X20
7005X25
Test
Com'l. Only
Com'l. Only
Symbol
Parameter
Condition
Version
Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating
CE
= V
IL
, Outputs Open
MIL.
S
--
--
--
--
160
370
155
340
mA
Current
SEM
= V
IH
L
--
--
--
--
150
320
145
280
(Both Ports Active) f = f
MAX
(3)
COM.
S
170
310
170
310
160
290
155
265
L
160
260
160
260
150
240
145
220
I
SB1
Standby Current
CE
L
=
CE
R
= V
IH
MIL.
S
--
--
--
--
20
90
16
80
mA
(Both Ports -- TTL
SEM
R
=
SEM
L
= V
IH
L
--
--
--
--
10
70
10
65
Level Inputs f = f
MAX
(3)
COM.
S
20
60
20
60
20
60
16
60
L
10
60
10
50
10
50
10
50
I
SB2
Standby Current
CE
"A"=
V
IL
and
CE
"B"=
V
IH
(5)
MIL.
S
--
--
--
--
95
240
90
215
mA
(One Port -- TTL Active Port Outputs Open
L
--
--
--
--
85
210
80
180
Level Inputs) f = f
MAX
(3)
COM.
S
105
190
105
190
95
180
90
170
SEM
R
=
SEM
L
> V
IH
L
95
160
95
160
85
150
80
140
I
SB3
Full Standby Current Both Ports
CE
L
and
MIL.
S
--
--
--
--
1.0
30
1.0
30
mA
(Both Ports -- All
CE
R
> V
CC
- 0.2V
(5)
L
--
--
--
--
0.2
10
0.2
10
CMOS Level Inputs) V
IN
> V
CC
- 0.2V or
COM.
S
1.0
15
1.0
15
1.0
15
1.0
15
V
IN
< 0.2V, f = 0
(4)
L
0.2
5
0.2
5
0.2
5
0.2
5
SEM
R
=
SEM
L
> V
CC
- 0.2V
I
SB4
Full Standby Current
CE"
B"
< 0.2V and
MIL.
S
--
--
--
--
90
225
85
200
mA
(One Port -- All
CE"
B"
> V
CC
- 0.2v
CMOS Level Inputs)
SEM
R
=
SEM
L
> V
CC
- 0.2V
L
--
--
--
--
80
200
75
170
V
IN
> V
CC
- 0.2V or
COM.
S
100
170
100
170
90
155
85
145
V
IN
< 0.2V
Active Port Outputs Open,
L
90
140
90
140
80
130
75
120
f = f
MAX
(3)
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
10%)
IDT7005S
IDT7005L
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
|I
LI
|
Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
--
10
--
5
A
|I
LO
|
Output Leakage Current
CE
= V
IH
, V
OUT
= 0V to V
CC
--
10
--
5
A
V
OL
Output Low Voltage
I
OL
= 4mA
--
0.4
--
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
--
2.4
--
V
NOTES:
2738 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25
C, and are not production tested. I
CC DC
= 120mA typ.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using "AC Test Conditions" of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
NOTE:
2738 tbl 08
1. At Vcc < 2.0V input leakages are undefined.